
Andrew W. Chriss
Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )
| Most Active Art Unit | 2472 |
| Art Unit(s) | 2419, 2472, 2609, 2479, 2619, 2400, 2416 |
| Total Applications | 328 |
| Issued Applications | 163 |
| Pending Applications | 87 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20167645
[patent_doc_number] => 20250259692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-14
[patent_title] => DEVICE DATA PATH MONITOR
[patent_app_type] => utility
[patent_app_number] => 18/830204
[patent_app_country] => US
[patent_app_date] => 2024-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3717
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830204
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/830204 | DEVICE DATA PATH MONITOR | Sep 9, 2024 | Pending |
Array
(
[id] => 19660599
[patent_doc_number] => 20240427664
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-26
[patent_title] => ERROR RATES FOR MEMORY WITH BUILT IN ERROR CORRECTION AND DETECTION
[patent_app_type] => utility
[patent_app_number] => 18/825345
[patent_app_country] => US
[patent_app_date] => 2024-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11008
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18825345
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/825345 | ERROR RATES FOR MEMORY WITH BUILT IN ERROR CORRECTION AND DETECTION | Sep 4, 2024 | Pending |
Array
(
[id] => 19662973
[patent_doc_number] => 20240430038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-26
[patent_title] => TERMINAL, BASE STATION, AND COMMUNICATION METHOD
[patent_app_type] => utility
[patent_app_number] => 18/824366
[patent_app_country] => US
[patent_app_date] => 2024-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23194
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18824366
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/824366 | TERMINAL, BASE STATION, AND COMMUNICATION METHOD | Sep 3, 2024 | Pending |
Array
(
[id] => 19645024
[patent_doc_number] => 20240419544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate
[patent_app_type] => utility
[patent_app_number] => 18/821886
[patent_app_country] => US
[patent_app_date] => 2024-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8918
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821886
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/821886 | Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate | Aug 29, 2024 | Pending |
Array
(
[id] => 19620240
[patent_doc_number] => 20240405920
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => INFORMATION PROCESSING APPARATUS, COMMUNICATION SYSTEM, INFORMATION PROCESSING METHOD AND PROGRAM
[patent_app_type] => utility
[patent_app_number] => 18/806709
[patent_app_country] => US
[patent_app_date] => 2024-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19638
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18806709
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/806709 | INFORMATION PROCESSING APPARATUS, COMMUNICATION SYSTEM, INFORMATION PROCESSING METHOD AND PROGRAM | Aug 15, 2024 | Pending |
Array
(
[id] => 19603094
[patent_doc_number] => 20240393974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => AUTHENTICATED STATELESS MOUNT STRING FOR A DISTRIBUTED FILE SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/795647
[patent_app_country] => US
[patent_app_date] => 2024-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6876
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18795647
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/795647 | AUTHENTICATED STATELESS MOUNT STRING FOR A DISTRIBUTED FILE SYSTEM | Aug 5, 2024 | Pending |
Array
(
[id] => 20580167
[patent_doc_number] => 12572418
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-10
[patent_title] => Machine-learning-based system health monitoring of a memory device
[patent_app_type] => utility
[patent_app_number] => 18/788635
[patent_app_country] => US
[patent_app_date] => 2024-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 4692
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788635
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/788635 | Machine-learning-based system health monitoring of a memory device | Jul 29, 2024 | Issued |
Array
(
[id] => 20513273
[patent_doc_number] => 20260037374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-02-05
[patent_title] => STORING STATUS INFORMATION USING REDUNDANT COLUMNS
[patent_app_type] => utility
[patent_app_number] => 18/789454
[patent_app_country] => US
[patent_app_date] => 2024-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4840
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789454
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/789454 | Storing status information using redundant columns | Jul 29, 2024 | Issued |
Array
(
[id] => 19588371
[patent_doc_number] => 20240385928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => DEEP NEURAL NETWORK IMPLEMENTATION FOR SOFT DECODING OF BCH CODE
[patent_app_type] => utility
[patent_app_number] => 18/787270
[patent_app_country] => US
[patent_app_date] => 2024-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25274
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787270
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/787270 | DEEP NEURAL NETWORK IMPLEMENTATION FOR SOFT DECODING OF BCH CODE | Jul 28, 2024 | Pending |
Array
(
[id] => 20501709
[patent_doc_number] => 20260031171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-29
[patent_title] => ARCHITECTURE FOR DETERMINISTIC MEMORY INITIALIZATION FOR AUTOMOTIVE ELECTRONICS
[patent_app_type] => utility
[patent_app_number] => 18/784704
[patent_app_country] => US
[patent_app_date] => 2024-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784704
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/784704 | ARCHITECTURE FOR DETERMINISTIC MEMORY INITIALIZATION FOR AUTOMOTIVE ELECTRONICS | Jul 24, 2024 | Pending |
Array
(
[id] => 20408864
[patent_doc_number] => 20250377973
[patent_country] => US
[patent_kind] => A2
[patent_issue_date] => 2025-12-11
[patent_title] => DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 18/777165
[patent_app_country] => US
[patent_app_date] => 2024-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17412
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777165
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/777165 | DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES | Jul 17, 2024 | Pending |
Array
(
[id] => 20408864
[patent_doc_number] => 20250377973
[patent_country] => US
[patent_kind] => A2
[patent_issue_date] => 2025-12-11
[patent_title] => DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 18/777165
[patent_app_country] => US
[patent_app_date] => 2024-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17412
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777165
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/777165 | DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES | Jul 17, 2024 | Pending |
Array
(
[id] => 20487445
[patent_doc_number] => 20260023644
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-22
[patent_title] => LOCKED RAID MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/775804
[patent_app_country] => US
[patent_app_date] => 2024-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775804
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/775804 | Locked raid memory devices | Jul 16, 2024 | Issued |
Array
(
[id] => 19985703
[patent_doc_number] => 20250123925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => PAGE-BY-PAGE LEVEL SHAPING
[patent_app_type] => utility
[patent_app_number] => 18/774464
[patent_app_country] => US
[patent_app_date] => 2024-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12917
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774464
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/774464 | PAGE-BY-PAGE LEVEL SHAPING | Jul 15, 2024 | Issued |
Array
(
[id] => 20550411
[patent_doc_number] => 12561204
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-24
[patent_title] => Method and system for on-ASIC error control encoding
[patent_app_type] => utility
[patent_app_number] => 18/772604
[patent_app_country] => US
[patent_app_date] => 2024-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 0
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772604
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/772604 | Method and system for on-ASIC error control encoding | Jul 14, 2024 | Issued |
Array
(
[id] => 20773412
[patent_doc_number] => 12657086
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-16
[patent_title] => Valley search in read error recovery for a memory device using low-density parity check syndrome weight and auto-read calibration
[patent_app_type] => utility
[patent_app_number] => 18/771829
[patent_app_country] => US
[patent_app_date] => 2024-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6284
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771829
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/771829 | Valley search in read error recovery for a memory device using low-density parity check syndrome weight and auto-read calibration | Jul 11, 2024 | Issued |
Array
(
[id] => 19978805
[patent_doc_number] => 12346280
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-01
[patent_title] => Multi-port media access channel (MAC) with flexible data-path width
[patent_app_type] => utility
[patent_app_number] => 18/770975
[patent_app_country] => US
[patent_app_date] => 2024-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 21
[patent_no_of_words] => 2157
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770975
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/770975 | Multi-port media access channel (MAC) with flexible data-path width | Jul 11, 2024 | Issued |
Array
(
[id] => 20482654
[patent_doc_number] => 12531130
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-20
[patent_title] => Non-volatile storage device offloading
[patent_app_type] => utility
[patent_app_number] => 18/758495
[patent_app_country] => US
[patent_app_date] => 2024-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 16430
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758495
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/758495 | Non-volatile storage device offloading | Jun 27, 2024 | Issued |
Array
(
[id] => 20365955
[patent_doc_number] => 20250355767
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-20
[patent_title] => NON-VOLATILE STORAGE DEVICE OFFLOADING IN A MULTI-DATA NODE ENVIRONMENT
[patent_app_type] => utility
[patent_app_number] => 18/758583
[patent_app_country] => US
[patent_app_date] => 2024-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13442
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758583
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/758583 | NON-VOLATILE STORAGE DEVICE OFFLOADING IN A MULTI-DATA NODE ENVIRONMENT | Jun 27, 2024 | Pending |
Array
(
[id] => 20027117
[patent_doc_number] => 20250165339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-22
[patent_title] => MEMORY CONTROLLER MANAGING READ LEVEL INFORMATION, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY CONTROLLER
[patent_app_type] => utility
[patent_app_number] => 18/753410
[patent_app_country] => US
[patent_app_date] => 2024-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7476
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753410
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/753410 | Memory controller managing read level information, memory system including the same, and operating method of the memory controller | Jun 24, 2024 | Issued |