Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2419, 2472, 2609, 2479, 2619, 2400, 2416
Total Applications
328
Issued Applications
163
Pending Applications
87
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15075217 [patent_doc_number] => 10467099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Controlled and verifiable information destruction [patent_app_type] => utility [patent_app_number] => 15/782193 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782193 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782193
Controlled and verifiable information destruction Oct 11, 2017 Issued
Array ( [id] => 15167499 [patent_doc_number] => 10489244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Systems and methods for detecting and correcting memory corruptions in software [patent_app_type] => utility [patent_app_number] => 15/723888 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15723888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/723888
Systems and methods for detecting and correcting memory corruptions in software Oct 2, 2017 Issued
Array ( [id] => 14065191 [patent_doc_number] => 10236911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Method and apparatus for encoding and decoding low density parity check codes [patent_app_type] => utility [patent_app_number] => 15/722335 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 26814 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722335
Method and apparatus for encoding and decoding low density parity check codes Oct 1, 2017 Issued
Array ( [id] => 14825305 [patent_doc_number] => 10409661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Slice metadata for optimized dispersed storage network memory storage strategies [patent_app_type] => utility [patent_app_number] => 15/720140 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6654 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720140
Slice metadata for optimized dispersed storage network memory storage strategies Sep 28, 2017 Issued
Array ( [id] => 12845248 [patent_doc_number] => 20180173589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => INTEGRATED SECURITY AND DATA REDUNDANCY [patent_app_type] => utility [patent_app_number] => 15/721329 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721329 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721329
Integrated security and data redundancy Sep 28, 2017 Issued
Array ( [id] => 12713191 [patent_doc_number] => 20180129563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MEMORY SYSTEM PERFORMING ERROR CORRECTION OF ADDRESS MAPPING TABLE [patent_app_type] => utility [patent_app_number] => 15/718143 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718143
Memory system performing error correction of address mapping table Sep 27, 2017 Issued
Array ( [id] => 12713191 [patent_doc_number] => 20180129563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MEMORY SYSTEM PERFORMING ERROR CORRECTION OF ADDRESS MAPPING TABLE [patent_app_type] => utility [patent_app_number] => 15/718143 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718143
Memory system performing error correction of address mapping table Sep 27, 2017 Issued
Array ( [id] => 12713191 [patent_doc_number] => 20180129563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MEMORY SYSTEM PERFORMING ERROR CORRECTION OF ADDRESS MAPPING TABLE [patent_app_type] => utility [patent_app_number] => 15/718143 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718143
Memory system performing error correction of address mapping table Sep 27, 2017 Issued
Array ( [id] => 12713191 [patent_doc_number] => 20180129563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MEMORY SYSTEM PERFORMING ERROR CORRECTION OF ADDRESS MAPPING TABLE [patent_app_type] => utility [patent_app_number] => 15/718143 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718143
Memory system performing error correction of address mapping table Sep 27, 2017 Issued
Array ( [id] => 14269307 [patent_doc_number] => 10284229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 64-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 15/706469 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6701 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706469 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/706469
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 64-symbol mapping, and bit interleaving method using same Sep 14, 2017 Issued
Array ( [id] => 14051245 [patent_doc_number] => 20190081730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => FORWARD ERROR CORRECTION WITH COMPRESSION CODING [patent_app_type] => utility [patent_app_number] => 15/703180 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703180
Forward error correction with compression coding Sep 12, 2017 Issued
Array ( [id] => 16299816 [patent_doc_number] => 20200285539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => QUANTUM ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 16/645756 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16645756 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/645756
Quantum error correction Sep 11, 2017 Issued
Array ( [id] => 14022543 [patent_doc_number] => 20190073265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => INCREMENTAL RAID STRIPE UPDATE PARITY CALCULATION [patent_app_type] => utility [patent_app_number] => 15/697566 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15697566 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/697566
Incremental RAID stripe update parity calculation Sep 6, 2017 Issued
Array ( [id] => 12234803 [patent_doc_number] => 20180067666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'Devices, systems, and methods for increasing endurance on a storage system having a plurality of components using adaptive code-rates' [patent_app_type] => utility [patent_app_number] => 15/732039 [patent_app_country] => US [patent_app_date] => 2017-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15732039 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/732039
Devices, systems, and methods for increasing endurance on a storage system having a plurality of components using adaptive code-rates Sep 5, 2017 Issued
Array ( [id] => 13843769 [patent_doc_number] => 20190025369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => DISPLAY DEVICE AND METHOD FOR DETECTING ELECTROSTATIC DISCHARGE PHENOMENON THEREOF [patent_app_type] => utility [patent_app_number] => 15/688884 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688884 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688884
DISPLAY DEVICE AND METHOD FOR DETECTING ELECTROSTATIC DISCHARGE PHENOMENON THEREOF Aug 28, 2017 Abandoned
Array ( [id] => 15075201 [patent_doc_number] => 10467091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Memory module, memory system including the same, and error correcting method thereof [patent_app_type] => utility [patent_app_number] => 15/689263 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15689263 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/689263
Memory module, memory system including the same, and error correcting method thereof Aug 28, 2017 Issued
Array ( [id] => 13449053 [patent_doc_number] => 20180276069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 15/690255 [patent_app_country] => US [patent_app_date] => 2017-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690255
Memory controller, memory system, and control method Aug 28, 2017 Issued
Array ( [id] => 12094482 [patent_doc_number] => 20170351575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'ERASURE CODING AND REPLICATION IN STORAGE CLUSTERS' [patent_app_type] => utility [patent_app_number] => 15/685833 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12616 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685833 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/685833
Erasure coding and replication in storage clusters Aug 23, 2017 Issued
Array ( [id] => 16676038 [patent_doc_number] => 20210064804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SYSTEM, APPARATUS AND METHOD FOR ADAPTIVE OPERATING VOLTAGE IN A FIELD PROGRAMMABLE GATE ARRAY (FPGA) [patent_app_type] => utility [patent_app_number] => 16/629600 [patent_app_country] => US [patent_app_date] => 2017-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16629600 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/629600
System, apparatus and method for adaptive operating voltage in a field programmable gate array (FPGA) Aug 22, 2017 Issued
Array ( [id] => 16211405 [patent_doc_number] => 20200244395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 16/637789 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16637789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/637789
Method and apparatus for using at least one redundancy version for transmission of a data unit Aug 9, 2017 Issued
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