
Andrew W. Chriss
Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )
| Most Active Art Unit | 2472 |
| Art Unit(s) | 2419, 2472, 2609, 2479, 2619, 2400, 2416 |
| Total Applications | 328 |
| Issued Applications | 163 |
| Pending Applications | 87 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11731249
[patent_doc_number] => 20170192692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'OPTIMIZING REBUILDS WHEN USING MULTIPLE INFORMATION DISPERSAL ALGORITHMS'
[patent_app_type] => utility
[patent_app_number] => 15/352950
[patent_app_country] => US
[patent_app_date] => 2016-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8275
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352950
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/352950 | Optimizing rebuilds when using multiple information dispersal algorithms | Nov 15, 2016 | Issued |
Array
(
[id] => 13891305
[patent_doc_number] => 10198199
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-05
[patent_title] => Applying multiple hash functions to generate multiple masked keys in a secure slice implementation
[patent_app_type] => utility
[patent_app_number] => 15/353166
[patent_app_country] => US
[patent_app_date] => 2016-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 7591
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353166
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/353166 | Applying multiple hash functions to generate multiple masked keys in a secure slice implementation | Nov 15, 2016 | Issued |
Array
(
[id] => 11665259
[patent_doc_number] => 20170153978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-01
[patent_title] => 'OPTIMIZED CACHING OF SLICES BY A DS PROCESSING UNIT'
[patent_app_type] => utility
[patent_app_number] => 15/353157
[patent_app_country] => US
[patent_app_date] => 2016-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9301
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353157
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/353157 | Optimized caching of slices by a DS processing unit | Nov 15, 2016 | Issued |
Array
(
[id] => 14269309
[patent_doc_number] => 10284230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-07
[patent_title] => Linked storage system and host system error correcting code
[patent_app_type] => utility
[patent_app_number] => 15/351620
[patent_app_country] => US
[patent_app_date] => 2016-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 7603
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351620
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/351620 | Linked storage system and host system error correcting code | Nov 14, 2016 | Issued |
Array
(
[id] => 12738286
[patent_doc_number] => 20180137929
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-17
[patent_title] => WEAR SENSOR AND METHOD OF OPERATION FOR A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/350669
[patent_app_country] => US
[patent_app_date] => 2016-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9765
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350669
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/350669 | WEAR SENSOR AND METHOD OF OPERATION FOR A MEMORY DEVICE | Nov 13, 2016 | Abandoned |
Array
(
[id] => 12155398
[patent_doc_number] => 20180026662
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-25
[patent_title] => 'METHOD FOR CONTROLLING DECODING PROCESS BASED ON PATH METRIC VALUE AND COMPUTING APPARATUS AND MOBILE DEVICE FOR CONTROLLING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/339264
[patent_app_country] => US
[patent_app_date] => 2016-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10043
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339264
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/339264 | Method for controlling decoding process based on path metric value and computing apparatus and mobile device for controlling the same | Oct 30, 2016 | Issued |
Array
(
[id] => 11845756
[patent_doc_number] => 09733307
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-08-15
[patent_title] => 'Optimized chain diagnostic fail isolation'
[patent_app_type] => utility
[patent_app_number] => 15/298699
[patent_app_country] => US
[patent_app_date] => 2016-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5606
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298699
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/298699 | Optimized chain diagnostic fail isolation | Oct 19, 2016 | Issued |
Array
(
[id] => 13120387
[patent_doc_number] => 10078547
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-18
[patent_title] => Predictive caching for check word snooping in high performance FICON
[patent_app_type] => utility
[patent_app_number] => 15/275651
[patent_app_country] => US
[patent_app_date] => 2016-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 16453
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275651
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/275651 | Predictive caching for check word snooping in high performance FICON | Sep 25, 2016 | Issued |
Array
(
[id] => 12549441
[patent_doc_number] => 10012693
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-03
[patent_title] => System on chip and secure debugging method
[patent_app_type] => utility
[patent_app_number] => 15/273869
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 5945
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273869
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/273869 | System on chip and secure debugging method | Sep 22, 2016 | Issued |
Array
(
[id] => 11747199
[patent_doc_number] => 20170201273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-13
[patent_title] => 'MULTI-LEVEL RAID-TYPE ENCODING WITH RANDOM CORRECTION CAPABILITY'
[patent_app_type] => utility
[patent_app_number] => 15/274109
[patent_app_country] => US
[patent_app_date] => 2016-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 15799
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274109
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/274109 | Multi-level raid-type encoding with random correction capability | Sep 22, 2016 | Issued |
Array
(
[id] => 11366057
[patent_doc_number] => 20170004038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-05
[patent_title] => 'SYSTEMS AND METHODS FOR ENHANCED DATA RECOVERY IN A SOLID STATE MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 15/269605
[patent_app_country] => US
[patent_app_date] => 2016-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7308
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15269605
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/269605 | Systems and methods for enhanced data recovery in a solid state memory system | Sep 18, 2016 | Issued |
Array
(
[id] => 11365364
[patent_doc_number] => 20170003345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-05
[patent_title] => 'INTEGRATED CIRCUIT CHIP AND A METHOD FOR TESTING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/267215
[patent_app_country] => US
[patent_app_date] => 2016-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 12534
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267215
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/267215 | Integrated circuit chip and a method for testing the same | Sep 15, 2016 | Issued |
Array
(
[id] => 14123283
[patent_doc_number] => 10248500
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Apparatuses and methods for generating probabilistic information with current integration sensing
[patent_app_type] => utility
[patent_app_number] => 15/267844
[patent_app_country] => US
[patent_app_date] => 2016-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7673
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267844
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/267844 | Apparatuses and methods for generating probabilistic information with current integration sensing | Sep 15, 2016 | Issued |
Array
(
[id] => 14123283
[patent_doc_number] => 10248500
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Apparatuses and methods for generating probabilistic information with current integration sensing
[patent_app_type] => utility
[patent_app_number] => 15/267844
[patent_app_country] => US
[patent_app_date] => 2016-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7673
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267844
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/267844 | Apparatuses and methods for generating probabilistic information with current integration sensing | Sep 15, 2016 | Issued |
Array
(
[id] => 14123283
[patent_doc_number] => 10248500
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Apparatuses and methods for generating probabilistic information with current integration sensing
[patent_app_type] => utility
[patent_app_number] => 15/267844
[patent_app_country] => US
[patent_app_date] => 2016-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7673
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267844
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/267844 | Apparatuses and methods for generating probabilistic information with current integration sensing | Sep 15, 2016 | Issued |
Array
(
[id] => 14123283
[patent_doc_number] => 10248500
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Apparatuses and methods for generating probabilistic information with current integration sensing
[patent_app_type] => utility
[patent_app_number] => 15/267844
[patent_app_country] => US
[patent_app_date] => 2016-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7673
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267844
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/267844 | Apparatuses and methods for generating probabilistic information with current integration sensing | Sep 15, 2016 | Issued |
Array
(
[id] => 11652629
[patent_doc_number] => 20170148529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF VERIFYING REPAIR RESULT OF MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/249928
[patent_app_country] => US
[patent_app_date] => 2016-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8567
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15249928
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/249928 | Memory device, memory system and method of verifying repair result of memory device | Aug 28, 2016 | Issued |
Array
(
[id] => 11316350
[patent_doc_number] => 20160352460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-01
[patent_title] => 'METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING PACKET IN A COMMUNICATION SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 15/234627
[patent_app_country] => US
[patent_app_date] => 2016-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 9214
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234627
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/234627 | Method and apparatus for transmitting and receiving packet in a communication system | Aug 10, 2016 | Issued |
Array
(
[id] => 11846455
[patent_doc_number] => 09734010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-15
[patent_title] => 'Data encoding in solid-state storage apparatus'
[patent_app_type] => utility
[patent_app_number] => 15/225856
[patent_app_country] => US
[patent_app_date] => 2016-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 11276
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225856
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/225856 | Data encoding in solid-state storage apparatus | Aug 1, 2016 | Issued |
Array
(
[id] => 12154525
[patent_doc_number] => 20180025789
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-25
[patent_title] => 'SHARED ERROR DETECTION AND CORRECTION MEMORY'
[patent_app_type] => utility
[patent_app_number] => 15/217719
[patent_app_country] => US
[patent_app_date] => 2016-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 9804
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15217719
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/217719 | Shared error detection and correction memory | Jul 21, 2016 | Issued |