Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2419, 2472, 2609, 2479, 2619, 2400, 2416
Total Applications
328
Issued Applications
163
Pending Applications
87
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10478252 [patent_doc_number] => 20150363269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'ERASURE CODING AND REPLICATION IN STORAGE CLUSTERS' [patent_app_type] => utility [patent_app_number] => 14/834017 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12558 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834017 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834017
Erasure coding and replication in storage clusters Aug 23, 2015 Issued
Array ( [id] => 10702191 [patent_doc_number] => 20160048338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'MEMORY BLOCK QUALITY IDENTIFICATION IN A MEMORY' [patent_app_type] => utility [patent_app_number] => 14/833849 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833849 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833849
Memory block quality identification in a memory Aug 23, 2015 Issued
Array ( [id] => 10697686 [patent_doc_number] => 20160043832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SECURE COMMUNICATION METHOD AND SYSTEM BASED ON BIT ERROR PROBABILITY' [patent_app_type] => utility [patent_app_number] => 14/820457 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15327 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820457 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/820457
Secure communication method and system based on bit error probability Aug 5, 2015 Issued
Array ( [id] => 11222352 [patent_doc_number] => 09450702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Method and apparatus for transmitting and receiving packet in a communication system' [patent_app_type] => utility [patent_app_number] => 14/811068 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 9191 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14811068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/811068
Method and apparatus for transmitting and receiving packet in a communication system Jul 27, 2015 Issued
Array ( [id] => 11752315 [patent_doc_number] => 09710327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Flash memory system and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/802833 [patent_app_country] => US [patent_app_date] => 2015-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9555 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14802833 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/802833
Flash memory system and operating method thereof Jul 16, 2015 Issued
Array ( [id] => 11397012 [patent_doc_number] => 20170017548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'Systems and Methods for Retaining Non-Converged Data Sets for Additional Processing' [patent_app_type] => utility [patent_app_number] => 14/800742 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8861 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800742 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800742
Systems and methods for retaining non-converged data sets for additional processing Jul 15, 2015 Issued
Array ( [id] => 11910169 [patent_doc_number] => 09778979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Storage device including error correction decoder and operating method of error correction decoder' [patent_app_type] => utility [patent_app_number] => 14/800012 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 17400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800012 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800012
Storage device including error correction decoder and operating method of error correction decoder Jul 14, 2015 Issued
Array ( [id] => 11832526 [patent_doc_number] => 09729279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Packet transmission and reception system, apparatus, and method' [patent_app_type] => utility [patent_app_number] => 14/800603 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800603 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800603
Packet transmission and reception system, apparatus, and method Jul 14, 2015 Issued
Array ( [id] => 11897981 [patent_doc_number] => 09767920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Semiconductor memory devices and memory systems including the same' [patent_app_type] => utility [patent_app_number] => 14/798634 [patent_app_country] => US [patent_app_date] => 2015-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 14785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798634 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/798634
Semiconductor memory devices and memory systems including the same Jul 13, 2015 Issued
Array ( [id] => 11638772 [patent_doc_number] => 09660765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-23 [patent_title] => 'Method and apparatus for broadcast information reception in wireless communication systems' [patent_app_type] => utility [patent_app_number] => 14/797671 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7134 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14797671 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/797671
Method and apparatus for broadcast information reception in wireless communication systems Jul 12, 2015 Issued
Array ( [id] => 11816823 [patent_doc_number] => 09720772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Memory system, method for controlling magnetic memory, and device for controlling magnetic memory' [patent_app_type] => utility [patent_app_number] => 14/796294 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5476 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14796294 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/796294
Memory system, method for controlling magnetic memory, and device for controlling magnetic memory Jul 9, 2015 Issued
Array ( [id] => 12169030 [patent_doc_number] => 09887806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Minimum latency link layer metaframing and error correction' [patent_app_type] => utility [patent_app_number] => 14/796792 [patent_app_country] => US [patent_app_date] => 2015-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9413 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14796792 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/796792
Minimum latency link layer metaframing and error correction Jul 9, 2015 Issued
Array ( [id] => 10667664 [patent_doc_number] => 20160013809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'PARITY CHECK MATRIX GENERATING METHOD, ENCODING APPARATUS, ENCODING METHOD, DECODING APPARATUS AND DECODING METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/794243 [patent_app_country] => US [patent_app_date] => 2015-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 20592 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14794243 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/794243
Parity check matrix generating method, encoding apparatus, encoding method, decoding apparatus and decoding method using the same Jul 7, 2015 Issued
Array ( [id] => 11924596 [patent_doc_number] => 09792179 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-17 [patent_title] => 'Eventually durable redundancy encoded data storage' [patent_app_type] => utility [patent_app_number] => 14/792031 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14473 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792031 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792031
Eventually durable redundancy encoded data storage Jul 5, 2015 Issued
Array ( [id] => 11056277 [patent_doc_number] => 20160253239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'DATA STORAGE DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/790787 [patent_app_country] => US [patent_app_date] => 2015-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6568 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14790787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/790787
DATA STORAGE DEVICE AND OPERATING METHOD THEREOF Jul 1, 2015 Abandoned
Array ( [id] => 10644169 [patent_doc_number] => 09361036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Correction of block errors for a system having non-volatile memory' [patent_app_type] => utility [patent_app_number] => 14/754468 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5923 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14754468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/754468
Correction of block errors for a system having non-volatile memory Jun 28, 2015 Issued
Array ( [id] => 10377688 [patent_doc_number] => 20150262695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING' [patent_app_type] => utility [patent_app_number] => 14/724065 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5873 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724065 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724065
Methods, devices, and systems for data sensing May 27, 2015 Issued
Array ( [id] => 11313209 [patent_doc_number] => 20160349318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'Dynamic Clock Chain Bypass' [patent_app_type] => utility [patent_app_number] => 14/721142 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721142 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721142
Dynamic Clock Chain Bypass May 25, 2015 Abandoned
Array ( [id] => 11919129 [patent_doc_number] => 09787326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Method and apparatus for encoding and decoding low density parity check codes' [patent_app_type] => utility [patent_app_number] => 14/716053 [patent_app_country] => US [patent_app_date] => 2015-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 28348 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14716053 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/716053
Method and apparatus for encoding and decoding low density parity check codes May 18, 2015 Issued
Array ( [id] => 12685633 [patent_doc_number] => 20180120377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => LOGIC ANALYZER AND PROBE THEREOF [patent_app_type] => utility [patent_app_number] => 15/326440 [patent_app_country] => US [patent_app_date] => 2015-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15326440 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/326440
LOGIC ANALYZER AND PROBE THEREOF May 17, 2015 Abandoned
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