
Andrew W. Chriss
Supervisory Patent Examiner (ID: 4510, Phone: (571)272-1774 , Office: P/2479 )
| Most Active Art Unit | 2472 |
| Art Unit(s) | 2472, 2400, 2416, 2609, 2479, 2619, 2419 |
| Total Applications | 298 |
| Issued Applications | 155 |
| Pending Applications | 86 |
| Abandoned Applications | 79 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20175711
[patent_doc_number] => 12394464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-19
[patent_title] => Hybrid FeRAM/OxRAM data storage circuit
[patent_app_type] => utility
[patent_app_number] => 18/379132
[patent_app_country] => US
[patent_app_date] => 2023-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 2114
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379132
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/379132 | Hybrid FeRAM/OxRAM data storage circuit | Oct 10, 2023 | Issued |
Array
(
[id] => 20188510
[patent_doc_number] => 12399622
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-26
[patent_title] => High-level architecture for 3D-NAND based in-memory search
[patent_app_type] => utility
[patent_app_number] => 18/378960
[patent_app_country] => US
[patent_app_date] => 2023-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 32
[patent_no_of_words] => 9155
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378960
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/378960 | High-level architecture for 3D-NAND based in-memory search | Oct 10, 2023 | Issued |
Array
(
[id] => 20175711
[patent_doc_number] => 12394464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-19
[patent_title] => Hybrid FeRAM/OxRAM data storage circuit
[patent_app_type] => utility
[patent_app_number] => 18/379132
[patent_app_country] => US
[patent_app_date] => 2023-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 2114
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379132
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/379132 | Hybrid FeRAM/OxRAM data storage circuit | Oct 10, 2023 | Issued |
Array
(
[id] => 20175711
[patent_doc_number] => 12394464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-19
[patent_title] => Hybrid FeRAM/OxRAM data storage circuit
[patent_app_type] => utility
[patent_app_number] => 18/379132
[patent_app_country] => US
[patent_app_date] => 2023-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 2114
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379132
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/379132 | Hybrid FeRAM/OxRAM data storage circuit | Oct 10, 2023 | Issued |
Array
(
[id] => 20175711
[patent_doc_number] => 12394464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-19
[patent_title] => Hybrid FeRAM/OxRAM data storage circuit
[patent_app_type] => utility
[patent_app_number] => 18/379132
[patent_app_country] => US
[patent_app_date] => 2023-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 2114
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379132
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/379132 | Hybrid FeRAM/OxRAM data storage circuit | Oct 10, 2023 | Issued |
Array
(
[id] => 18958665
[patent_doc_number] => 20240046992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => ELECTRICAL FUSE ONE TIME PROGRAMMABLE (OTP) MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/482053
[patent_app_country] => US
[patent_app_date] => 2023-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9551
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482053
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/482053 | Electrical fuse one time programmable (OTP) memory | Oct 5, 2023 | Issued |
Array
(
[id] => 18958665
[patent_doc_number] => 20240046992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => ELECTRICAL FUSE ONE TIME PROGRAMMABLE (OTP) MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/482053
[patent_app_country] => US
[patent_app_date] => 2023-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9551
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18482053
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/482053 | Electrical fuse one time programmable (OTP) memory | Oct 5, 2023 | Issued |
Array
(
[id] => 20274671
[patent_doc_number] => 12444455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Memory structure
[patent_app_type] => utility
[patent_app_number] => 18/376455
[patent_app_country] => US
[patent_app_date] => 2023-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2341
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376455
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/376455 | Memory structure | Oct 3, 2023 | Issued |
Array
(
[id] => 19749186
[patent_doc_number] => 20250037751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => MEMORY DEVICES CONFIGURED WITH ADAPTIVE WORD LINE PULSE ADJUSTMENT AND METHODS FOR OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/479300
[patent_app_country] => US
[patent_app_date] => 2023-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11807
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479300
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/479300 | MEMORY DEVICES CONFIGURED WITH ADAPTIVE WORD LINE PULSE ADJUSTMENT AND METHODS FOR OPERATING THE SAME | Oct 1, 2023 | Pending |
Array
(
[id] => 19972216
[patent_doc_number] => 12340834
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-24
[patent_title] => Memory devices having a random number generator for protecting memory cells, and methods for protecting memory devices
[patent_app_type] => utility
[patent_app_number] => 18/374151
[patent_app_country] => US
[patent_app_date] => 2023-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6420
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374151
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/374151 | Memory devices having a random number generator for protecting memory cells, and methods for protecting memory devices | Sep 27, 2023 | Issued |
Array
(
[id] => 19679108
[patent_doc_number] => 12190979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Dynamic random access memory built-in self-test power fail mitigation
[patent_app_type] => utility
[patent_app_number] => 18/373658
[patent_app_country] => US
[patent_app_date] => 2023-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5525
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373658
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/373658 | Dynamic random access memory built-in self-test power fail mitigation | Sep 26, 2023 | Issued |
Array
(
[id] => 18900585
[patent_doc_number] => 20240016070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-11
[patent_title] => MEMORY CELL, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF MEMORY CELL
[patent_app_type] => utility
[patent_app_number] => 18/472161
[patent_app_country] => US
[patent_app_date] => 2023-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9213
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472161
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/472161 | Memory cell, integrated circuit, and manufacturing method of memory cell | Sep 20, 2023 | Issued |
Array
(
[id] => 19434480
[patent_doc_number] => 20240302978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => MEMORY CONTROLLER AND MEMORY SYSTEM WITH DATA STROBE SIGNAL CALIBRATION CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/469394
[patent_app_country] => US
[patent_app_date] => 2023-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7658
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469394
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/469394 | Memory controller and memory system with data strobe signal calibration circuit | Sep 17, 2023 | Issued |
Array
(
[id] => 20359945
[patent_doc_number] => 12475949
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-18
[patent_title] => Non-volatile memory with efficient precharge in sub-block mode
[patent_app_type] => utility
[patent_app_number] => 18/468349
[patent_app_country] => US
[patent_app_date] => 2023-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 24
[patent_no_of_words] => 14241
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468349
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/468349 | Non-volatile memory with efficient precharge in sub-block mode | Sep 14, 2023 | Issued |
Array
(
[id] => 20080621
[patent_doc_number] => 12354696
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 18/463686
[patent_app_country] => US
[patent_app_date] => 2023-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 76
[patent_figures_cnt] => 76
[patent_no_of_words] => 11034
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463686
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/463686 | Semiconductor memory device | Sep 7, 2023 | Issued |
Array
(
[id] => 19054420
[patent_doc_number] => 20240096389
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 18/459962
[patent_app_country] => US
[patent_app_date] => 2023-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10098
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459962
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/459962 | Nonvolatile semiconductor memory and manufacturing method therefor | Aug 31, 2023 | Issued |
Array
(
[id] => 19054420
[patent_doc_number] => 20240096389
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 18/459962
[patent_app_country] => US
[patent_app_date] => 2023-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10098
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459962
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/459962 | Nonvolatile semiconductor memory and manufacturing method therefor | Aug 31, 2023 | Issued |
Array
(
[id] => 18823053
[patent_doc_number] => 20230397394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => METHOD FOR PRODUCING MEMORY DEVICE USING PILLAR-SHAPED SEMICONDUCTOR ELEMENTS
[patent_app_type] => utility
[patent_app_number] => 18/234996
[patent_app_country] => US
[patent_app_date] => 2023-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12961
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234996
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/234996 | METHOD FOR PRODUCING MEMORY DEVICE USING PILLAR-SHAPED SEMICONDUCTOR ELEMENTS | Aug 16, 2023 | Pending |
Array
(
[id] => 19626838
[patent_doc_number] => 12165685
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-10
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/233349
[patent_app_country] => US
[patent_app_date] => 2023-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 51
[patent_no_of_words] => 33294
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233349
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/233349 | Semiconductor device | Aug 13, 2023 | Issued |
Array
(
[id] => 18812658
[patent_doc_number] => 20230386995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => STORAGE SYSTEM INCLUDING A DECOUPLING DEVICE HAVING A PLURALITY OF UNIT CAPACITORS
[patent_app_type] => utility
[patent_app_number] => 18/446959
[patent_app_country] => US
[patent_app_date] => 2023-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7664
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446959
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/446959 | Storage system including a decoupling device having a plurality of unit capacitors | Aug 8, 2023 | Issued |