
Andrew W. Chriss
Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )
| Most Active Art Unit | 2472 |
| Art Unit(s) | 2419, 2472, 2609, 2479, 2619, 2400, 2416 |
| Total Applications | 328 |
| Issued Applications | 163 |
| Pending Applications | 87 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19391457
[patent_doc_number] => 20240281327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR STORING AND ACCESSING MEMORY METADATA AND ERROR CORRECTION CODE DATA
[patent_app_type] => utility
[patent_app_number] => 18/441830
[patent_app_country] => US
[patent_app_date] => 2024-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8481
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441830
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/441830 | Apparatuses, systems, and methods for storing and accessing memory metadata and error correction code data | Feb 13, 2024 | Issued |
Array
(
[id] => 19481089
[patent_doc_number] => 20240329131
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => TEST SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/438993
[patent_app_country] => US
[patent_app_date] => 2024-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7431
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438993
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/438993 | Test system | Feb 11, 2024 | Issued |
Array
(
[id] => 19204796
[patent_doc_number] => 20240176695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-30
[patent_title] => DYNAMIC CONTROL OF ERROR MANAGEMENT AND SIGNALING
[patent_app_type] => utility
[patent_app_number] => 18/435652
[patent_app_country] => US
[patent_app_date] => 2024-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22063
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435652
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/435652 | Dynamic control of error management and signaling | Feb 6, 2024 | Issued |
Array
(
[id] => 20274691
[patent_doc_number] => 12444475
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Reducing read error handling operations during power up of a memory device
[patent_app_type] => utility
[patent_app_number] => 18/431279
[patent_app_country] => US
[patent_app_date] => 2024-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2503
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431279
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/431279 | Reducing read error handling operations during power up of a memory device | Feb 1, 2024 | Issued |
Array
(
[id] => 19362871
[patent_doc_number] => 20240264905
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => EEPROM EMULATION METHOD
[patent_app_type] => utility
[patent_app_number] => 18/430259
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3104
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430259
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/430259 | EEPROM emulation method | Jan 31, 2024 | Issued |
Array
(
[id] => 19467705
[patent_doc_number] => 20240321375
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => Configurable Testing and Repair System for Non-Volatile Memory
[patent_app_type] => utility
[patent_app_number] => 18/428471
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3668
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428471
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/428471 | Configurable testing and repair system for non-volatile memory | Jan 30, 2024 | Issued |
Array
(
[id] => 20434281
[patent_doc_number] => 12505010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-23
[patent_title] => Method of transmitting and receiving image signals and image processing device for implementing the same
[patent_app_type] => utility
[patent_app_number] => 18/425637
[patent_app_country] => US
[patent_app_date] => 2024-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425637
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/425637 | Method of transmitting and receiving image signals and image processing device for implementing the same | Jan 28, 2024 | Issued |
Array
(
[id] => 19320246
[patent_doc_number] => 20240241790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => DETERMINING LOCATIONS IN NAND MEMORY FOR BOOT-UP CODE
[patent_app_type] => utility
[patent_app_number] => 18/420888
[patent_app_country] => US
[patent_app_date] => 2024-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19125
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420888
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/420888 | Determining locations in NAND memory for boot-up code | Jan 23, 2024 | Issued |
Array
(
[id] => 19174562
[patent_doc_number] => 20240160536
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => INFRASTRUCTURE BACKUP AND RECOVERY
[patent_app_type] => utility
[patent_app_number] => 18/420486
[patent_app_country] => US
[patent_app_date] => 2024-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16085
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420486
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/420486 | Infrastructure backup and recovery | Jan 22, 2024 | Issued |
Array
(
[id] => 19174552
[patent_doc_number] => 20240160526
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => DATA RECOVERY USING ORDERED DATA REQUESTS
[patent_app_type] => utility
[patent_app_number] => 18/416967
[patent_app_country] => US
[patent_app_date] => 2024-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25390
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416967
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/416967 | Data recovery using ordered data requests | Jan 18, 2024 | Issued |
Array
(
[id] => 19949867
[patent_doc_number] => 12321229
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Burst correction reed solomon decoding for memory applications
[patent_app_type] => utility
[patent_app_number] => 18/415632
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2046
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415632
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/415632 | Burst correction reed solomon decoding for memory applications | Jan 16, 2024 | Issued |
Array
(
[id] => 19514234
[patent_doc_number] => 20240345920
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => DECODER FOR BURST CORRECTION READ SOLOMON DECODING FOR MEMORY APPLICATIONS
[patent_app_type] => utility
[patent_app_number] => 18/415634
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7115
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415634
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/415634 | Decoder for burst correction read Solomon decoding for memory applications | Jan 16, 2024 | Issued |
Array
(
[id] => 20689345
[patent_doc_number] => 12619494
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-05
[patent_title] => Storage device and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 18/414475
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 0
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414475
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/414475 | Storage device and operating method thereof | Jan 16, 2024 | Issued |
Array
(
[id] => 19933511
[patent_doc_number] => 12306715
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2025-05-20
[patent_title] => Min-sum decoding for irregular low-density parity check codes in memory devices
[patent_app_type] => utility
[patent_app_number] => 18/410939
[patent_app_country] => US
[patent_app_date] => 2024-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 937
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410939
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/410939 | Min-sum decoding for irregular low-density parity check codes in memory devices | Jan 10, 2024 | Issued |
Array
(
[id] => 19320244
[patent_doc_number] => 20240241788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => TECHNIQUES FOR MANAGING MEMORY EXCEPTION HANDLING
[patent_app_type] => utility
[patent_app_number] => 18/397399
[patent_app_country] => US
[patent_app_date] => 2023-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14406
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397399
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/397399 | Techniques for managing memory exception handling | Dec 26, 2023 | Issued |
Array
(
[id] => 19906953
[patent_doc_number] => 12283974
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-22
[patent_title] => System and method for distribution storage of blockchain transaction data based on erasure code
[patent_app_type] => utility
[patent_app_number] => 18/397612
[patent_app_country] => US
[patent_app_date] => 2023-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 1177
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397612
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/397612 | System and method for distribution storage of blockchain transaction data based on erasure code | Dec 26, 2023 | Issued |
Array
(
[id] => 20160073
[patent_doc_number] => 12386701
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-12
[patent_title] => Memory chips and operating methods thereof
[patent_app_type] => utility
[patent_app_number] => 18/544555
[patent_app_country] => US
[patent_app_date] => 2023-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544555
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/544555 | Memory chips and operating methods thereof | Dec 18, 2023 | Issued |
Array
(
[id] => 20228491
[patent_doc_number] => 12417143
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-16
[patent_title] => Memory system, method of operating the same, and electronic system including the same
[patent_app_type] => utility
[patent_app_number] => 18/543737
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 30
[patent_no_of_words] => 8938
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543737
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/543737 | Memory system, method of operating the same, and electronic system including the same | Dec 17, 2023 | Issued |
Array
(
[id] => 20052081
[patent_doc_number] => 20250190303
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-12
[patent_title] => MEMORY DEVICE PPR FAILURE HANDLING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/537401
[patent_app_country] => US
[patent_app_date] => 2023-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1171
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537401
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/537401 | Memory device PPR failure handling system | Dec 11, 2023 | Issued |
Array
(
[id] => 20304131
[patent_doc_number] => 12450119
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-21
[patent_title] => Minimizing redundancy for stuck bit coding
[patent_app_type] => utility
[patent_app_number] => 18/533655
[patent_app_country] => US
[patent_app_date] => 2023-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 0
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533655
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/533655 | Minimizing redundancy for stuck bit coding | Dec 7, 2023 | Issued |