Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2419, 2472, 2609, 2479, 2619, 2400, 2416
Total Applications
328
Issued Applications
163
Pending Applications
87
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20388156 [patent_doc_number] => 12487882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => System and method for protecting data using cyclic properties of error correcting code [patent_app_type] => utility [patent_app_number] => 18/530955 [patent_app_country] => US [patent_app_date] => 2023-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 3010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530955
System and method for protecting data using cyclic properties of error correcting code Dec 5, 2023 Issued
Array ( [id] => 19204801 [patent_doc_number] => 20240176700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => OPERATION METHOD OF STORAGE CONTROLLER FOR NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/512613 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512613
Operation method of storage controller for nonvolatile memory device Nov 16, 2023 Issued
Array ( [id] => 19174613 [patent_doc_number] => 20240160587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => MEMORY SYSTEM WITH CACHED MEMORY MODULE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/513246 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513246
Memory system with cached memory module operations Nov 16, 2023 Issued
Array ( [id] => 20203961 [patent_doc_number] => 12406744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Memory controller, storage device, and operating method of storage device [patent_app_type] => utility [patent_app_number] => 18/506184 [patent_app_country] => US [patent_app_date] => 2023-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18506184 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/506184
Memory controller, storage device, and operating method of storage device Nov 9, 2023 Issued
Array ( [id] => 18989773 [patent_doc_number] => 20240061742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => Error Checking For Systolic Array Computation [patent_app_type] => utility [patent_app_number] => 18/386641 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/386641
Error checking for systolic array computation Nov 2, 2023 Issued
Array ( [id] => 18991858 [patent_doc_number] => 20240063827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => BUTTERFLY NETWORK ON LOAD DATA RETURN [patent_app_type] => utility [patent_app_number] => 18/498196 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498196 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/498196
Butterfly network on load data return Oct 30, 2023 Issued
Array ( [id] => 18991848 [patent_doc_number] => 20240063817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => LDPC CODE MATRICES [patent_app_type] => utility [patent_app_number] => 18/497131 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497131 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/497131
LDPC code matrices Oct 29, 2023 Issued
Array ( [id] => 18959039 [patent_doc_number] => 20240047366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SEMICONDUCTOR DEVICE AND DATA TRANSFERRING METHOD FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/489308 [patent_app_country] => US [patent_app_date] => 2023-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18489308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/489308
Semiconductor device and data transferring method for semiconductor device Oct 17, 2023 Issued
Array ( [id] => 19084826 [patent_doc_number] => 20240111627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => COORDINATED ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/379057 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/379057
Coordinated error correction Oct 10, 2023 Issued
Array ( [id] => 19334368 [patent_doc_number] => 20240248798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => QUANTUM ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/481796 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481796 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/481796
Quantum error correction Oct 4, 2023 Issued
Array ( [id] => 19101716 [patent_doc_number] => 20240120944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => APPARATUS AND METHOD FOR PROCESSING RECEIVE DATA IN A RECEIVE DATA PATH INCLUDING PARALLEL FEC DECODING [patent_app_type] => utility [patent_app_number] => 18/481359 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481359 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/481359
Apparatus and method for processing receive data in a receive data path including parallel FEC decoding Oct 4, 2023 Issued
Array ( [id] => 20494601 [patent_doc_number] => 12536473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Handoff sequence for city nodes [patent_app_type] => utility [patent_app_number] => 18/481944 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 40695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481944 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/481944
Handoff sequence for city nodes Oct 4, 2023 Issued
Array ( [id] => 18907586 [patent_doc_number] => 20240023071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => COMMUNICATION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/475850 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475850 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475850
Communication method and apparatus Sep 26, 2023 Issued
Array ( [id] => 19053165 [patent_doc_number] => 20240095134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY MODULE WITH DEDICATED REPAIR DEVICES [patent_app_type] => utility [patent_app_number] => 18/373219 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373219
Memory module with dedicated repair devices Sep 25, 2023 Issued
Array ( [id] => 18899452 [patent_doc_number] => 20240014937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => INFORMATION PROCESSING APPARATUS, COMMUNICATION SYSTEM, INFORMATION PROCESSING METHOD AND PROGRAM [patent_app_type] => utility [patent_app_number] => 18/372153 [patent_app_country] => US [patent_app_date] => 2023-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18372153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/372153
Information processing apparatus, communication system, information processing method and program Sep 24, 2023 Issued
Array ( [id] => 19686332 [patent_doc_number] => 20250004877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => ERROR CORRECTION METHOD, MEMORY SYSTEM AND MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/473972 [patent_app_country] => US [patent_app_date] => 2023-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473972 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/473972
Error correction method, memory system and memory controller Sep 24, 2023 Issued
Array ( [id] => 19434655 [patent_doc_number] => 20240303153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => ERROR CORRECTION CIRCUIT CAPABLE OF AUTOMATICALLY COMPENSATING FOR CLOCK MARGIN AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/472682 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472682 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/472682
Error correction circuit capable of automatically compensating for clock margin and method of operating the same Sep 21, 2023 Issued
Array ( [id] => 19733575 [patent_doc_number] => 12211575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Storage device executing read retry operation based on read retry sequence key and operating method of the storage device [patent_app_type] => utility [patent_app_number] => 18/472751 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8623 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472751 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/472751
Storage device executing read retry operation based on read retry sequence key and operating method of the storage device Sep 21, 2023 Issued
Array ( [id] => 19546153 [patent_doc_number] => 20240363189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => CONTROLLER, MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/471307 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18471307 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/471307
Controller, memory system and operating method of memory system Sep 20, 2023 Issued
Array ( [id] => 20132782 [patent_doc_number] => 12375100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Labeling for higher order modulation polar codes [patent_app_type] => utility [patent_app_number] => 18/471123 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15898 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18471123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/471123
Labeling for higher order modulation polar codes Sep 19, 2023 Issued
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