Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 4510, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2472, 2400, 2416, 2609, 2479, 2619, 2419
Total Applications
298
Issued Applications
155
Pending Applications
86
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19435734 [patent_doc_number] => 20240304232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => MEMORY DEVICE CAPABLE OF PERFORMING IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 18/178958 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178958 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178958
Memory device capable of performing in-memory computing Mar 5, 2023 Issued
Array ( [id] => 18472727 [patent_doc_number] => 20230207015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => MEMORY DEVICE AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/114935 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18114935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/114935
Memory device and programming method thereof Feb 26, 2023 Issued
Array ( [id] => 18475553 [patent_doc_number] => 20230209841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => CROSSBAR ARRAY CIRCUIT WITH PARALLEL GROUNDING LINES [patent_app_type] => utility [patent_app_number] => 18/170837 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170837 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170837
Crossbar array circuit with parallel grounding lines Feb 16, 2023 Issued
Array ( [id] => 19525731 [patent_doc_number] => 12127489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Integrated circuit structure [patent_app_type] => utility [patent_app_number] => 18/170947 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170947
Integrated circuit structure Feb 16, 2023 Issued
Array ( [id] => 18572632 [patent_doc_number] => 20230262970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/109086 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109086
Semiconductor storage device Feb 12, 2023 Issued
Array ( [id] => 18572632 [patent_doc_number] => 20230262970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/109086 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109086
Semiconductor storage device Feb 12, 2023 Issued
Array ( [id] => 19446384 [patent_doc_number] => 12096699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Magnetoresistive effect element [patent_app_type] => utility [patent_app_number] => 18/167325 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11402 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/167325
Magnetoresistive effect element Feb 9, 2023 Issued
Array ( [id] => 19858050 [patent_doc_number] => 12260900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => In-memory computing circuit and method, and semiconductor memory [patent_app_type] => utility [patent_app_number] => 18/166435 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 21246 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166435 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166435
In-memory computing circuit and method, and semiconductor memory Feb 7, 2023 Issued
Array ( [id] => 18438184 [patent_doc_number] => 20230185479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => MEMORY SUB-SYSTEM REFRESH [patent_app_type] => utility [patent_app_number] => 18/105043 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105043
Memory sub-system refresh Feb 1, 2023 Issued
Array ( [id] => 18542793 [patent_doc_number] => 20230247911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => TWO-DIMENSIONAL SEMICONDUCTOR STRUCTURE WITH CONTROLLABLE MAGNETIC STATE AND FERROMAGNETIC RESONANCE [patent_app_type] => utility [patent_app_number] => 18/103290 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103290 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103290
TWO-DIMENSIONAL SEMICONDUCTOR STRUCTURE WITH CONTROLLABLE MAGNETIC STATE AND FERROMAGNETIC RESONANCE Jan 29, 2023 Pending
Array ( [id] => 18542793 [patent_doc_number] => 20230247911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => TWO-DIMENSIONAL SEMICONDUCTOR STRUCTURE WITH CONTROLLABLE MAGNETIC STATE AND FERROMAGNETIC RESONANCE [patent_app_type] => utility [patent_app_number] => 18/103290 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103290 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103290
TWO-DIMENSIONAL SEMICONDUCTOR STRUCTURE WITH CONTROLLABLE MAGNETIC STATE AND FERROMAGNETIC RESONANCE Jan 29, 2023 Pending
Array ( [id] => 19951078 [patent_doc_number] => 12322448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Memory device and operating method of the memory device [patent_app_type] => utility [patent_app_number] => 18/101954 [patent_app_country] => US [patent_app_date] => 2023-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 6245 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101954 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101954
Memory device and operating method of the memory device Jan 25, 2023 Issued
Array ( [id] => 18787865 [patent_doc_number] => 20230376234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => 3D MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/100110 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100110
3D memory circuit Jan 22, 2023 Issued
Array ( [id] => 18379421 [patent_doc_number] => 20230154510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/154726 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154726
Memory device Jan 12, 2023 Issued
Array ( [id] => 18865582 [patent_doc_number] => 20230420019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => DATA RECEIVING CIRCUIT, DATA RECEIVING SYSTEM, AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/152919 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152919
Data receiving circuit, data receiving system, and memory device Jan 10, 2023 Issued
Array ( [id] => 18351480 [patent_doc_number] => 20230139591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => MEMORIES HAVING SPLIT-GATE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/091433 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091433 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091433
Memories having split-gate memory cells Dec 29, 2022 Issued
Array ( [id] => 18366615 [patent_doc_number] => 20230148206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => METHOD FOR READING MEMORY DEVICE AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/090454 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090454
Method for reading memory device and memory device Dec 27, 2022 Issued
Array ( [id] => 19626891 [patent_doc_number] => 12165738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => SRAM non-clamping write driver with write assist [patent_app_type] => utility [patent_app_number] => 18/086423 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5855 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18086423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/086423
SRAM non-clamping write driver with write assist Dec 20, 2022 Issued
Array ( [id] => 18472684 [patent_doc_number] => 20230206972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => CIRCUIT AND METHOD FOR SETTING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/069226 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/069226
Setting module and setting method thereof for synchronous dynamic random access memory Dec 19, 2022 Issued
Array ( [id] => 19672842 [patent_doc_number] => 12185639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Antiferromagnetic memory device featuring tunneling magnetoresistance readout and current-induced writing of information [patent_app_type] => utility [patent_app_number] => 18/068213 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068213 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068213
Antiferromagnetic memory device featuring tunneling magnetoresistance readout and current-induced writing of information Dec 18, 2022 Issued
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