Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2419, 2472, 2609, 2479, 2619, 2400, 2416
Total Applications
328
Issued Applications
163
Pending Applications
87
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19588367 [patent_doc_number] => 20240385924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => DEVICE TRIMMING VIA DIRECT MEMORY ACCESS [patent_app_type] => utility [patent_app_number] => 18/345449 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345449
Device trimming via direct memory access Jun 29, 2023 Issued
Array ( [id] => 19522608 [patent_doc_number] => 12124331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Interface circuit and memory controller [patent_app_type] => utility [patent_app_number] => 18/215796 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11011 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215796 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/215796
Interface circuit and memory controller Jun 27, 2023 Issued
Array ( [id] => 19442867 [patent_doc_number] => 12093131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit [patent_app_type] => utility [patent_app_number] => 18/215181 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11122 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215181 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/215181
Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit Jun 27, 2023 Issued
Array ( [id] => 19609933 [patent_doc_number] => 12158806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-03 [patent_title] => Efficient estimation of threshold voltage distributions in a nonvolatile memory [patent_app_type] => utility [patent_app_number] => 18/341807 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7558 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18341807 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/341807
Efficient estimation of threshold voltage distributions in a nonvolatile memory Jun 26, 2023 Issued
Array ( [id] => 18925446 [patent_doc_number] => 20240028450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => BIT AND SIGNAL LEVEL MAPPING [patent_app_type] => utility [patent_app_number] => 18/213728 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213728 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213728
Bit and signal level mapping Jun 22, 2023 Issued
Array ( [id] => 18943375 [patent_doc_number] => 20240038514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => BAYESIAN DECREMENTAL SCHEME FOR CHARGE STATE DECONVOLUTION [patent_app_type] => utility [patent_app_number] => 18/337183 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337183
Bayesian decremental scheme for charge state deconvolution Jun 18, 2023 Issued
Array ( [id] => 20203078 [patent_doc_number] => 12405857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Methods and systems for raid protection in zoned solid-state drives [patent_app_type] => utility [patent_app_number] => 18/209613 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 2734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209613
Methods and systems for raid protection in zoned solid-state drives Jun 13, 2023 Issued
Array ( [id] => 18712596 [patent_doc_number] => 20230335229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => STRUCTURED DATA GENERATION METHOD AND APPARATUS, DEVICE, MEDIUM, AND PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 18/333140 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333140
Structured data generation method and apparatus, device, medium, and program product Jun 11, 2023 Issued
Array ( [id] => 18659918 [patent_doc_number] => 20230305925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SOFT ERROR DETECTION AND CORRECTION FOR DATA STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/325370 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325370 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325370
Soft error detection and correction for data storage devices May 29, 2023 Issued
Array ( [id] => 19506482 [patent_doc_number] => 12117902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 18/324226 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13441 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324226
Memory system May 25, 2023 Issued
Array ( [id] => 19152533 [patent_doc_number] => 11977444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Methods for error count reporting with scaled error count information, and memory devices employing the same [patent_app_type] => utility [patent_app_number] => 18/200439 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200439 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200439
Methods for error count reporting with scaled error count information, and memory devices employing the same May 21, 2023 Issued
Array ( [id] => 19427030 [patent_doc_number] => 12086452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Authenticated stateless mount string for a distributed file system [patent_app_type] => utility [patent_app_number] => 18/314374 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6909 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314374 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314374
Authenticated stateless mount string for a distributed file system May 8, 2023 Issued
Array ( [id] => 18599986 [patent_doc_number] => 20230274787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => METHOD TO INCREASE THE USABLE WORD WIDTH OF A MEMORY PROVIDING AN ERROR CORRECTION SCHEME [patent_app_type] => utility [patent_app_number] => 18/313669 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313669 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313669
Method to increase the usable word width of a memory providing an error correction scheme May 7, 2023 Issued
Array ( [id] => 18586667 [patent_doc_number] => 20230268932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => ETHERNET CODING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/309014 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309014 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309014
Ethernet coding method and apparatus Apr 27, 2023 Issued
Array ( [id] => 18727953 [patent_doc_number] => 20230342246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR CHIP FOR CORRECTING ALIGNED ERROR, SEMICONDUCTOR SYSTEM FOR CORRECTING ALIGNED ERROR, AND METHOD FOR CORRECTING ALIGNED ERROR [patent_app_type] => utility [patent_app_number] => 18/139440 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139440
Semiconductor chip for correcting aligned error, semiconductor system for correcting aligned error, and method for correcting aligned error Apr 25, 2023 Issued
Array ( [id] => 19312996 [patent_doc_number] => 12038808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Memory integrity check [patent_app_type] => utility [patent_app_number] => 18/305497 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4795 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305497
Memory integrity check Apr 23, 2023 Issued
Array ( [id] => 19924567 [patent_doc_number] => 12298847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Tracking host-provided metadata in a memory sub-system [patent_app_type] => utility [patent_app_number] => 18/299532 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/299532
Tracking host-provided metadata in a memory sub-system Apr 11, 2023 Issued
Array ( [id] => 18555048 [patent_doc_number] => 20230253064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => IMPRINT MANAGEMENT FOR MEMORY [patent_app_type] => utility [patent_app_number] => 18/129585 [patent_app_country] => US [patent_app_date] => 2023-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 66779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18129585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/129585
Imprint management for memory Mar 30, 2023 Issued
Array ( [id] => 18513103 [patent_doc_number] => 20230229328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => Systems, Methods, and Computer Readable Media Providing Arbitrary Sizing of Data Extents [patent_app_type] => utility [patent_app_number] => 18/191985 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191985 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/191985
Systems, methods, and computer readable media providing arbitrary sizing of data extents Mar 28, 2023 Issued
Array ( [id] => 19391294 [patent_doc_number] => 20240281164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHOD FOR SIGNALING MEMORY REQUIREMENTS IN ATSC3.0 WHEN OUT-OF-ORDER DATA IS BEING UTILIZED [patent_app_type] => utility [patent_app_number] => 18/186808 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/186808
Method for signaling memory requirements in ATSC3.0 when out-of-order data is being utilized Mar 19, 2023 Issued
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