Angela J Lee

Array ( [id] => 16759594 [patent_doc_number] => 10978149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Resistive memory apparatus and adjusting method for write-in voltage thereof [patent_app_type] => utility [patent_app_number] => 16/872374 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3499 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16872374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16455772 [patent_doc_number] => 20200365198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/930078 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17107233 [patent_doc_number] => 11127458 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => Non-uniform state spacing in multi-state memory element for low-power operation [patent_app_type] => utility [patent_app_number] => 16/861204 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16578441 [patent_doc_number] => 20210012842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => METHOD AND CIRCUIT FOR PROVIDING AUXILIARY POWER AND STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/846648 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16637321 [patent_doc_number] => 10915832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Constructing and programming quantum hardware for robust quantum annealing processes [patent_app_type] => utility [patent_app_number] => 16/841251 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16378559 [patent_doc_number] => 20200327401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => COMPUTING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/838495 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115313 [patent_doc_number] => 20210295910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MEMORY OPERATION WITH DOUBLE-SIDED ASYMMETRIC DECODERS [patent_app_type] => utility [patent_app_number] => 16/824104 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17599075 [patent_doc_number] => 20220148649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => AREA-EFFICIENT DUAL-PORT AND MULTI-PORT SRAM. AREA-EFFICIENT MEMORY CELL FOR SRAM. [patent_app_type] => utility [patent_app_number] => 17/438574 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17438574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17660463 [patent_doc_number] => 20220180928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => STORAGE APPARATUS AND STORAGE CONTROL APPARATUS [patent_app_type] => utility [patent_app_number] => 17/601153 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17601153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16578453 [patent_doc_number] => 20210012854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME [patent_app_type] => utility [patent_app_number] => 16/813796 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16827547 [patent_doc_number] => 20210142840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => Self-activated Bias Generator [patent_app_type] => utility [patent_app_number] => 16/810245 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17152272 [patent_doc_number] => 11145359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Reduced retention leakage SRAM [patent_app_type] => utility [patent_app_number] => 16/809006 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7790 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17018187 [patent_doc_number] => 11087832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Three-dimensional nanoribbon-based static random-access memory [patent_app_type] => utility [patent_app_number] => 16/806283 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 18958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17637919 [patent_doc_number] => 11348648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/804019 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8669 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17660462 [patent_doc_number] => 20220180927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => STORAGE DEVICE AND STORAGE CONTROL DEVICE [patent_app_type] => utility [patent_app_number] => 17/601146 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17601146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16759593 [patent_doc_number] => 10978148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Hybrid sensing scheme compensating for cell resistance instability [patent_app_type] => utility [patent_app_number] => 16/784512 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18804107 [patent_doc_number] => 11837270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Ferroelectric memory and memory element thereof [patent_app_type] => utility [patent_app_number] => 17/436777 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7441 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17436777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16204321 [patent_doc_number] => 20200237311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => SIGNAL PROCESSING DEVICE AND SIGNAL PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/751110 [patent_app_country] => US [patent_app_date] => 2020-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16751110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16417595 [patent_doc_number] => 10825495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal [patent_app_type] => utility [patent_app_number] => 16/735543 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8881 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16119209 [patent_doc_number] => 20200211627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => Semiconductor Device and Method for Driving Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/732555 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732555 [rel_patent_id] =>[rel_patent_doc_number] =>)