Search

Angela J Lee

Examiner (ID: 10714, Phone: (571)272-4453 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2911
Total Applications
4543
Issued Applications
4500
Pending Applications
13
Abandoned Applications
25

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16609054 [patent_doc_number] => 10910067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 16/297789 [patent_app_country] => US [patent_app_date] => 2019-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 60 [patent_no_of_words] => 26809 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16297789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/297789
Memory system Mar 10, 2019 Issued
Array ( [id] => 16707468 [patent_doc_number] => 10957410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Methods and apparatus for facilitated program and erase of two-terminal memory devices [patent_app_type] => utility [patent_app_number] => 16/291396 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291396
Methods and apparatus for facilitated program and erase of two-terminal memory devices Mar 3, 2019 Issued
Array ( [id] => 16307079 [patent_doc_number] => 10775865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Memory system including a nonvolatile memory and a volatile memory, and method [patent_app_type] => utility [patent_app_number] => 16/290004 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16290004 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/290004
Memory system including a nonvolatile memory and a volatile memory, and method Feb 28, 2019 Issued
Array ( [id] => 16280390 [patent_doc_number] => 10763433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Asymmetric correlated electron switch operation [patent_app_type] => utility [patent_app_number] => 16/284901 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 9278 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16284901 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/284901
Asymmetric correlated electron switch operation Feb 24, 2019 Issued
Array ( [id] => 15299499 [patent_doc_number] => 20190392885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => 3D Memory Array Clusters and Resulting Memory Architecture [patent_app_type] => utility [patent_app_number] => 16/226554 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226554
3D memory array clusters and resulting memory architecture Dec 18, 2018 Issued
Array ( [id] => 17309984 [patent_doc_number] => 11211108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Ferroelectric memory device [patent_app_type] => utility [patent_app_number] => 16/226356 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226356
Ferroelectric memory device Dec 18, 2018 Issued
Array ( [id] => 16447931 [patent_doc_number] => 10839862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Cross point array memory in a non-volatile dual in-line memory module [patent_app_type] => utility [patent_app_number] => 16/226626 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8640 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226626
Cross point array memory in a non-volatile dual in-line memory module Dec 18, 2018 Issued
Array ( [id] => 16095155 [patent_doc_number] => 20200201564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => MEMORY MODULE INTERFACES [patent_app_type] => utility [patent_app_number] => 16/225559 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16225559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/225559
Memory module interfaces Dec 18, 2018 Issued
Array ( [id] => 16080167 [patent_doc_number] => 20200194070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => APPARATUS AND METHODS FOR PROGRAMMING MEMORY CELLS USING MULTI-STEP PROGRAMMING PULSES [patent_app_type] => utility [patent_app_number] => 16/223305 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223305
Apparatus and methods for programming memory cells using multi-step programming pulses Dec 17, 2018 Issued
Array ( [id] => 16218251 [patent_doc_number] => 10734071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Multi-level cell programming using optimized multiphase mapping with balanced Gray code [patent_app_type] => utility [patent_app_number] => 16/219825 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9274 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219825
Multi-level cell programming using optimized multiphase mapping with balanced Gray code Dec 12, 2018 Issued
Array ( [id] => 15400735 [patent_doc_number] => 10541027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Multifunctional memory cells [patent_app_type] => utility [patent_app_number] => 16/218125 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 18478 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/218125
Multifunctional memory cells Dec 11, 2018 Issued
Array ( [id] => 15425921 [patent_doc_number] => 10545889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-28 [patent_title] => High-speed low VT drift receiver [patent_app_type] => utility [patent_app_number] => 16/215603 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215603
High-speed low VT drift receiver Dec 9, 2018 Issued
Array ( [id] => 14163551 [patent_doc_number] => 20190108878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => REFLOW PROTECTION [patent_app_type] => utility [patent_app_number] => 16/209152 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209152
Reflow protection Dec 3, 2018 Issued
Array ( [id] => 14110437 [patent_doc_number] => 20190096894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => Memory Cells and Memory Arrays [patent_app_type] => utility [patent_app_number] => 16/204409 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204409 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204409
Memory cells and memory arrays Nov 28, 2018 Issued
Array ( [id] => 15047003 [patent_doc_number] => 20190334506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => LEVEL SHIFTER AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/202521 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202521 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202521
Level shifter and memory system including the same Nov 27, 2018 Issued
Array ( [id] => 15045101 [patent_doc_number] => 20190333555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => SEMICONDUCTOR SYSTEM, SEMICONDUCTOR CHIP, AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR SYSTEM [patent_app_type] => utility [patent_app_number] => 16/203351 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203351
Semiconductor system, semiconductor chip, and semiconductor memory system including the semiconductor system Nov 27, 2018 Issued
Array ( [id] => 14382711 [patent_doc_number] => 20190165268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => RESISTIVE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/200853 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200853 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/200853
Operation method of resistive memory device Nov 26, 2018 Issued
Array ( [id] => 14348471 [patent_doc_number] => 20190156208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => NEURAL NETWORKS USING CROSS-POINT ARRAY AND PATTERN READOUT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/197651 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197651
Neural networks using cross-point array and pattern readout method thereof Nov 20, 2018 Issued
Array ( [id] => 15427377 [patent_doc_number] => 10546623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Resistive memory device having memory cell array and system including the same [patent_app_type] => utility [patent_app_number] => 16/195199 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16195199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/195199
Resistive memory device having memory cell array and system including the same Nov 18, 2018 Issued
Array ( [id] => 15856795 [patent_doc_number] => 10643690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Transposable feedback field-effect electronic device and array circuit using the same [patent_app_type] => utility [patent_app_number] => 16/181419 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8690 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181419
Transposable feedback field-effect electronic device and array circuit using the same Nov 5, 2018 Issued
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