Angela J Lee
Examiner (ID: 10714, Phone: (571)272-4453 , Office: P/2911 )
Most Active Art Unit | 2911 |
Art Unit(s) | 2911 |
Total Applications | 4543 |
Issued Applications | 4500 |
Pending Applications | 13 |
Abandoned Applications | 25 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16739036
[patent_doc_number] => 10964702
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-30
[patent_title] => Semiconductor device with first-in-first-out circuit
[patent_app_type] => utility
[patent_app_number] => 16/163471
[patent_app_country] => US
[patent_app_date] => 2018-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 8708
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163471
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/163471 | Semiconductor device with first-in-first-out circuit | Oct 16, 2018 | Issued |
Array
(
[id] => 15516559
[patent_doc_number] => 10564864
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-02-18
[patent_title] => Method for estimating data retention time in a solid state drive
[patent_app_type] => utility
[patent_app_number] => 16/151750
[patent_app_country] => US
[patent_app_date] => 2018-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 5575
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16151750
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/151750 | Method for estimating data retention time in a solid state drive | Oct 3, 2018 | Issued |
Array
(
[id] => 16926951
[patent_doc_number] => 11048434
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-29
[patent_title] => Compute in memory circuits with time-to-digital computation
[patent_app_type] => utility
[patent_app_number] => 16/147024
[patent_app_country] => US
[patent_app_date] => 2018-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 20983
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147024
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/147024 | Compute in memory circuits with time-to-digital computation | Sep 27, 2018 | Issued |
Array
(
[id] => 13847429
[patent_doc_number] => 20190027199
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-24
[patent_title] => APPARATUSES AND METHODS FOR DETERMINING A PHASE RELATIONSHIP BETWEEN AN INPUT CLOCK SIGNAL AND A MULTIPHASE CLOCK SIGNAL
[patent_app_type] => utility
[patent_app_number] => 16/143082
[patent_app_country] => US
[patent_app_date] => 2018-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8830
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143082
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/143082 | Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal | Sep 25, 2018 | Issued |
Array
(
[id] => 14800683
[patent_doc_number] => 10403349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-03
[patent_title] => Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells
[patent_app_type] => utility
[patent_app_number] => 16/140281
[patent_app_country] => US
[patent_app_date] => 2018-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 15746
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140281
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/140281 | Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells | Sep 23, 2018 | Issued |
Array
(
[id] => 14784307
[patent_doc_number] => 20190267051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/117633
[patent_app_country] => US
[patent_app_date] => 2018-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117633
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/117633 | Semiconductor devices and semiconductor systems including a semiconductor device | Aug 29, 2018 | Issued |
Array
(
[id] => 13740101
[patent_doc_number] => 20180374520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-27
[patent_title] => Signal Conversion
[patent_app_type] => utility
[patent_app_number] => 16/117509
[patent_app_country] => US
[patent_app_date] => 2018-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5458
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117509
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/117509 | Signal conversion based on complimentary analog signal pairs | Aug 29, 2018 | Issued |
Array
(
[id] => 15702985
[patent_doc_number] => 10607679
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-31
[patent_title] => Memory device and refreshing method thereof
[patent_app_type] => utility
[patent_app_number] => 16/115569
[patent_app_country] => US
[patent_app_date] => 2018-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9158
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16115569
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/115569 | Memory device and refreshing method thereof | Aug 28, 2018 | Issued |
Array
(
[id] => 15487961
[patent_doc_number] => 10559335
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-11
[patent_title] => Method of training drive strength, ODT of memory device, computing system performing the same and system-on-chip performing the same
[patent_app_type] => utility
[patent_app_number] => 16/116369
[patent_app_country] => US
[patent_app_date] => 2018-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9817
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116369
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/116369 | Method of training drive strength, ODT of memory device, computing system performing the same and system-on-chip performing the same | Aug 28, 2018 | Issued |
Array
(
[id] => 14445909
[patent_doc_number] => 20190180828
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD THEREOF AND OUTPUT METHOD OF DATA STROBE SIGNAL
[patent_app_type] => utility
[patent_app_number] => 16/111219
[patent_app_country] => US
[patent_app_date] => 2018-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111219
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/111219 | Semiconductor memory device, manufacturing method thereof and output method of data strobe signal | Aug 23, 2018 | Issued |
Array
(
[id] => 15532109
[patent_doc_number] => 20200058360
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-20
[patent_title] => Floating Boosted Pre-Charge Scheme for Sense Amplifiers
[patent_app_type] => utility
[patent_app_number] => 16/104001
[patent_app_country] => US
[patent_app_date] => 2018-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6531
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104001
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/104001 | Floating boosted pre-charge scheme for sense amplifiers | Aug 15, 2018 | Issued |
Array
(
[id] => 14752511
[patent_doc_number] => 20190259429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => MEMORY DEVICE DETERMINING OPERATION MODE BASED ON EXTERNAL VOLTAGE AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/103261
[patent_app_country] => US
[patent_app_date] => 2018-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9432
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103261
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/103261 | Memory device determining operation mode based on external voltage and method of operating the same | Aug 13, 2018 | Issued |
Array
(
[id] => 15375375
[patent_doc_number] => 10529413
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-07
[patent_title] => Semiconductor device and method for driving semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/103157
[patent_app_country] => US
[patent_app_date] => 2018-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 81
[patent_no_of_words] => 36673
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 409
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103157
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/103157 | Semiconductor device and method for driving semiconductor device | Aug 13, 2018 | Issued |
Array
(
[id] => 14572899
[patent_doc_number] => 20190214057
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-11
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/103059
[patent_app_country] => US
[patent_app_date] => 2018-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12927
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -31
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103059
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/103059 | Semiconductor device with memory banks and sense amplifier arrays | Aug 13, 2018 | Issued |
Array
(
[id] => 14984589
[patent_doc_number] => 10446214
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-10-15
[patent_title] => Sense amplifier with split capacitors
[patent_app_type] => utility
[patent_app_number] => 16/102053
[patent_app_country] => US
[patent_app_date] => 2018-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 19335
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102053
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/102053 | Sense amplifier with split capacitors | Aug 12, 2018 | Issued |
Array
(
[id] => 13613055
[patent_doc_number] => 20180358077
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => FERROELECTRIC MEMORY CELL SENSING
[patent_app_type] => utility
[patent_app_number] => 16/059727
[patent_app_country] => US
[patent_app_date] => 2018-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12524
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059727
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/059727 | Ferroelectric memory cell sensing | Aug 8, 2018 | Issued |
Array
(
[id] => 14366429
[patent_doc_number] => 10304526
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-28
[patent_title] => Semiconductor integrated circuit device and system
[patent_app_type] => utility
[patent_app_number] => 16/059255
[patent_app_country] => US
[patent_app_date] => 2018-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 37
[patent_no_of_words] => 29469
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059255
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/059255 | Semiconductor integrated circuit device and system | Aug 8, 2018 | Issued |
Array
(
[id] => 15461411
[patent_doc_number] => 20200043530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-06
[patent_title] => BANK AND CHANNEL STRUCTURE OF STACKED SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/051445
[patent_app_country] => US
[patent_app_date] => 2018-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6563
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051445
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/051445 | Bank and channel structure of stacked semiconductor device | Jul 30, 2018 | Issued |
Array
(
[id] => 15061023
[patent_doc_number] => 10460823
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-29
[patent_title] => Test control circuit, semiconductor memory apparatus and semiconductor system using the test control circuit
[patent_app_type] => utility
[patent_app_number] => 16/037631
[patent_app_country] => US
[patent_app_date] => 2018-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6542
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037631
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/037631 | Test control circuit, semiconductor memory apparatus and semiconductor system using the test control circuit | Jul 16, 2018 | Issued |
Array
(
[id] => 13542773
[patent_doc_number] => 20180322933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-08
[patent_title] => MEMORY DEVICES AND APPARATUS CONFIGURED TO APPLY POSITIVE VOLTAGE LEVELS TO DATA LINES FOR MEMORY CELLS SELECTED FOR AND INHIBITED FROM PROGRAMMING
[patent_app_type] => utility
[patent_app_number] => 16/035857
[patent_app_country] => US
[patent_app_date] => 2018-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7051
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035857
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/035857 | Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming | Jul 15, 2018 | Issued |