Angela J Lee
Examiner (ID: 10714, Phone: (571)272-4453 , Office: P/2911 )
Most Active Art Unit | 2911 |
Art Unit(s) | 2911 |
Total Applications | 4543 |
Issued Applications | 4500 |
Pending Applications | 13 |
Abandoned Applications | 25 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 12147398
[patent_doc_number] => 09881655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-30
[patent_title] => 'Memory circuit having data lines selectively coupled to a sense amplifier and method for operating the same'
[patent_app_type] => utility
[patent_app_number] => 14/929511
[patent_app_country] => US
[patent_app_date] => 2015-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4291
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14929511
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/929511 | Memory circuit having data lines selectively coupled to a sense amplifier and method for operating the same | Nov 1, 2015 | Issued |
Array
(
[id] => 11539278
[patent_doc_number] => 09613693
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-04-04
[patent_title] => 'Methods for setting a resistance of programmable resistance memory cells and devices including the same'
[patent_app_type] => utility
[patent_app_number] => 14/927352
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 6123
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14927352
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/927352 | Methods for setting a resistance of programmable resistance memory cells and devices including the same | Oct 28, 2015 | Issued |
Array
(
[id] => 11417406
[patent_doc_number] => 09564238
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-02-07
[patent_title] => 'Flash memory system using memory cell as source line pull down circuit'
[patent_app_type] => utility
[patent_app_number] => 14/919005
[patent_app_country] => US
[patent_app_date] => 2015-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3715
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14919005
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/919005 | Flash memory system using memory cell as source line pull down circuit | Oct 20, 2015 | Issued |
Array
(
[id] => 10747191
[patent_doc_number] => 20160093342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-31
[patent_title] => 'PORTABLE STORAGE DEVICE THAT CAN CHECK MEMORY FREE SPACE'
[patent_app_type] => utility
[patent_app_number] => 14/872023
[patent_app_country] => US
[patent_app_date] => 2015-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3561
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872023
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/872023 | Portable storage device that can check memory free space | Sep 29, 2015 | Issued |
Array
(
[id] => 17785905
[patent_doc_number] => 11409023
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-09
[patent_title] => Methods to handle discontinuity in constructing design space using moving least squares
[patent_app_type] => utility
[patent_app_number] => 14/868548
[patent_app_country] => US
[patent_app_date] => 2015-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 9356
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868548
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/868548 | Methods to handle discontinuity in constructing design space using moving least squares | Sep 28, 2015 | Issued |
Array
(
[id] => 11532364
[patent_doc_number] => 20170092342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-30
[patent_title] => 'TECHNOLOGIES FOR CLEARING A PAGE OF MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/866579
[patent_app_country] => US
[patent_app_date] => 2015-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 12962
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866579
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/866579 | Technologies for clearing a page of memory | Sep 24, 2015 | Issued |
Array
(
[id] => 11510002
[patent_doc_number] => 09601165
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-03-21
[patent_title] => 'Sense amplifier'
[patent_app_type] => utility
[patent_app_number] => 14/864702
[patent_app_country] => US
[patent_app_date] => 2015-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8442
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864702
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/864702 | Sense amplifier | Sep 23, 2015 | Issued |
Array
(
[id] => 11532380
[patent_doc_number] => 20170092358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-30
[patent_title] => 'CONTENT ADDRESSABLE MEMORY WITH AN ORDERED SEQUENCE'
[patent_app_type] => utility
[patent_app_number] => 14/863711
[patent_app_country] => US
[patent_app_date] => 2015-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6740
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863711
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/863711 | Content addressable memory with an ordered sequence | Sep 23, 2015 | Issued |
Array
(
[id] => 12040223
[patent_doc_number] => 09818458
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-11-14
[patent_title] => 'Techniques for entry to a lower power state for a memory device'
[patent_app_type] => utility
[patent_app_number] => 14/862269
[patent_app_country] => US
[patent_app_date] => 2015-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 10559
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862269
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/862269 | Techniques for entry to a lower power state for a memory device | Sep 22, 2015 | Issued |
Array
(
[id] => 11503216
[patent_doc_number] => 20170077400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-16
[patent_title] => 'ASYMMETRIC CORRELATED ELECTRON SWITCH OPERATION'
[patent_app_type] => utility
[patent_app_number] => 14/850213
[patent_app_country] => US
[patent_app_date] => 2015-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9651
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850213
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/850213 | Asymmetric correlated electron switch operation | Sep 9, 2015 | Issued |
Array
(
[id] => 10495049
[patent_doc_number] => 20150380071
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'CIRCUIT AND METHOD FOR IMPRINT REDUCTION IN FRAM MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 14/846350
[patent_app_country] => US
[patent_app_date] => 2015-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5948
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846350
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/846350 | Circuit and method for imprint reduction in FRAM memories | Sep 3, 2015 | Issued |
Array
(
[id] => 10492957
[patent_doc_number] => 20150377978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'SECONDARY BATTERY STATE DETECTING DEVICE AND SECONDARY BATTERY STATE DETECTING METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/846682
[patent_app_country] => US
[patent_app_date] => 2015-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5353
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846682
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/846682 | Secondary battery state detecting device and secondary battery state detecting method | Sep 3, 2015 | Issued |
Array
(
[id] => 11214994
[patent_doc_number] => 09444036
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-09-13
[patent_title] => 'Implementing segregated media based magnetic memory'
[patent_app_type] => utility
[patent_app_number] => 14/835543
[patent_app_country] => US
[patent_app_date] => 2015-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 52
[patent_no_of_words] => 6398
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835543
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/835543 | Implementing segregated media based magnetic memory | Aug 24, 2015 | Issued |
Array
(
[id] => 10470272
[patent_doc_number] => 20150355288
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-10
[patent_title] => 'SECONDARY BATTERY DEGRADATION DETERMINATION METHOD AND SECONDARY BATTERY DEGRADATION DETERMINATION DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/829035
[patent_app_country] => US
[patent_app_date] => 2015-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7481
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829035
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/829035 | Secondary battery degradation determination method and secondary battery degradation determination device | Aug 17, 2015 | Issued |
Array
(
[id] => 10652446
[patent_doc_number] => 09368715
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-14
[patent_title] => 'Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM)'
[patent_app_type] => utility
[patent_app_number] => 14/822295
[patent_app_country] => US
[patent_app_date] => 2015-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9558
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822295
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/822295 | Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM) | Aug 9, 2015 | Issued |
Array
(
[id] => 12115197
[patent_doc_number] => 09871193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-16
[patent_title] => 'Methods of producing and controlling tunneling electroresistance and tunneling magnetoresistance in a multiferroic tunnel junction'
[patent_app_type] => utility
[patent_app_number] => 14/818075
[patent_app_country] => US
[patent_app_date] => 2015-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 27
[patent_no_of_words] => 10909
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14818075
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/818075 | Methods of producing and controlling tunneling electroresistance and tunneling magnetoresistance in a multiferroic tunnel junction | Aug 3, 2015 | Issued |
Array
(
[id] => 10455070
[patent_doc_number] => 20150340085
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-26
[patent_title] => 'TRACKING BIT CELL AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/817269
[patent_app_country] => US
[patent_app_date] => 2015-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7532
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14817269
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/817269 | Tracking bit cell and method | Aug 3, 2015 | Issued |
Array
(
[id] => 10440264
[patent_doc_number] => 20150325276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS'
[patent_app_type] => utility
[patent_app_number] => 14/801700
[patent_app_country] => US
[patent_app_date] => 2015-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8875
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14801700
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/801700 | Bipolar logic gates on MOS-based memory chips | Jul 15, 2015 | Issued |
Array
(
[id] => 11328026
[patent_doc_number] => 20160358637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-08
[patent_title] => 'MULTI-BANK MEMORY WITH LINE TRACKING LOOP'
[patent_app_type] => utility
[patent_app_number] => 14/751820
[patent_app_country] => US
[patent_app_date] => 2015-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 12738
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751820
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/751820 | Multi-bank memory with line tracking loop | Jun 25, 2015 | Issued |
Array
(
[id] => 11483064
[patent_doc_number] => 09589615
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-07
[patent_title] => 'Digitally trimmable integrated resistors including resistive memory elements'
[patent_app_type] => utility
[patent_app_number] => 14/750670
[patent_app_country] => US
[patent_app_date] => 2015-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 9429
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750670
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/750670 | Digitally trimmable integrated resistors including resistive memory elements | Jun 24, 2015 | Issued |