Angela J Lee

Array ( [id] => 18774014 [patent_doc_number] => 20230368844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => PRE-READ CYCLE TIMING SHRINK BY SGD BIAS CONTROL AND PAGE AND WORDLINE CONTROL [patent_app_type] => utility [patent_app_number] => 17/741580 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18080776 [patent_doc_number] => 20220406388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SETTING SWITCHING FOR SINGLE-LEVEL CELLS [patent_app_type] => utility [patent_app_number] => 17/736902 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19376446 [patent_doc_number] => 12068024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Address dependent wordline timing in asynchronous static random access memory [patent_app_type] => utility [patent_app_number] => 17/734045 [patent_app_country] => US [patent_app_date] => 2022-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5027 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18950769 [patent_doc_number] => 11894072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture [patent_app_type] => utility [patent_app_number] => 17/724769 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 16898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17992952 [patent_doc_number] => 20220358989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Methods and Circuits for Power Management of a Memory Module [patent_app_type] => utility [patent_app_number] => 17/725026 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18123381 [patent_doc_number] => 20230008991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => MEMORY AND METHOD FOR WRITING MEMOERY [patent_app_type] => utility [patent_app_number] => 17/659951 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18401912 [patent_doc_number] => 11664056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Method and apparatus for accessing to data in response to power-supply event [patent_app_type] => utility [patent_app_number] => 17/723989 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18827480 [patent_doc_number] => 11842769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Memory circuit with leakage current blocking mechanism and memory device having the memory circuit [patent_app_type] => utility [patent_app_number] => 17/721207 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18679474 [patent_doc_number] => 20230317130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => RESISTIVE MEMORY ARRAY WITH LOCALIZED REFERENCE CELLS [patent_app_type] => utility [patent_app_number] => 17/709525 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18679503 [patent_doc_number] => 20230317159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => RESISTIVE MEMORY WITH ENHANCED REDUNDANCY WRITING [patent_app_type] => utility [patent_app_number] => 17/709662 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17722558 [patent_doc_number] => 20220215280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => CONSTRUCTING AND PROGRAMMING QUANTUM HARDWARE FOR ROBUST QUANTUM ANNEALING PROCESSES [patent_app_type] => utility [patent_app_number] => 17/706158 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17708258 [patent_doc_number] => 20220208266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => ADAPTIVE MEMORY CELL WRITE CONDITIONS [patent_app_type] => utility [patent_app_number] => 17/698808 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17691867 [patent_doc_number] => 20220199160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating [patent_app_type] => utility [patent_app_number] => 17/693751 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18309304 [patent_doc_number] => 20230113204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => DUTY CORRECTION DEVICE INCLUDING DUTY CORRECTION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING DUTY CORRECTION DEVICE [patent_app_type] => utility [patent_app_number] => 17/690932 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168245 [patent_doc_number] => 11984156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Nonvolatile memory devices having pumping circuits operable in multiple modes [patent_app_type] => utility [patent_app_number] => 17/679530 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6842 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18486804 [patent_doc_number] => 20230214150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => READ VOLTAGE LEVEL CORRECTION METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 17/679109 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18950774 [patent_doc_number] => 11894077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Self-diagnostic smart verify algorithm in user mode to prevent unreliable acquired smart verify program voltage [patent_app_type] => utility [patent_app_number] => 17/678584 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 16210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18570235 [patent_doc_number] => 20230260572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => ELECTRONIC CIRCUITS, MEMORY DEVICES, AND METHODS FOR OPERATING AN ELECTRONIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/672312 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18639252 [patent_doc_number] => 11763868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Sub-wordline driver [patent_app_type] => utility [patent_app_number] => 17/671536 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9218 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19427956 [patent_doc_number] => 12087384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Bias voltage generation circuit for memory devices [patent_app_type] => utility [patent_app_number] => 17/668962 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3210 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668962 [rel_patent_id] =>[rel_patent_doc_number] =>)