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Angela J Lee

Examiner (ID: 10714, Phone: (571)272-4453 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2911
Total Applications
4543
Issued Applications
4500
Pending Applications
13
Abandoned Applications
25

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18669727 [patent_doc_number] => 11776637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Voltage sharing across memory dies in response to a charge pump failure [patent_app_type] => utility [patent_app_number] => 17/592237 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 12158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592237 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/592237
Voltage sharing across memory dies in response to a charge pump failure Feb 2, 2022 Issued
Array ( [id] => 18827485 [patent_doc_number] => 11842774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Memories for calibrating sensing of memory cell data states [patent_app_type] => utility [patent_app_number] => 17/583537 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 15262 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583537 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583537
Memories for calibrating sensing of memory cell data states Jan 24, 2022 Issued
Array ( [id] => 18333122 [patent_doc_number] => 20230125070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => MULTILEVEL MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/578113 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578113
MULTILEVEL MEMORY DEVICE AND METHOD Jan 17, 2022 Pending
Array ( [id] => 18935224 [patent_doc_number] => 11887662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Matrix of elementary switches forming a message, associated reading and writing methods [patent_app_type] => utility [patent_app_number] => 17/575045 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6711 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575045 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575045
Matrix of elementary switches forming a message, associated reading and writing methods Jan 12, 2022 Issued
Array ( [id] => 17566308 [patent_doc_number] => 20220130457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => REFLOW PROTECTION [patent_app_type] => utility [patent_app_number] => 17/572209 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572209
Reflow protection Jan 9, 2022 Issued
Array ( [id] => 17566299 [patent_doc_number] => 20220130448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => STATE DETECTION CIRCUIT FOR ANTI-FUSE MEMORY CELL, AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/570476 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570476
State detection circuit for anti-fuse memory cell, and memory Jan 6, 2022 Issued
Array ( [id] => 18488133 [patent_doc_number] => 20230215481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => MEMORY CELL, MEMORY DEVICE AND METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/568158 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568158
Preconditioning operation for a memory cell with a spontaneously-polarizable memory element Jan 3, 2022 Issued
Array ( [id] => 18639277 [patent_doc_number] => 11763893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/568336 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 60 [patent_no_of_words] => 26824 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568336
Memory system Jan 3, 2022 Issued
Array ( [id] => 17551311 [patent_doc_number] => 20220122653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => MODE-DEPENDENT HEATING OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/564993 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564993
Mode-dependent heating of a memory device Dec 28, 2021 Issued
Array ( [id] => 18721256 [patent_doc_number] => 11798608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Techniques to perform a sense operation [patent_app_type] => utility [patent_app_number] => 17/646259 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13510 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646259
Techniques to perform a sense operation Dec 27, 2021 Issued
Array ( [id] => 17917161 [patent_doc_number] => 20220319557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => Low Power Scheme for Power Down in Integrated Dual Rail SRAMs [patent_app_type] => utility [patent_app_number] => 17/549962 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549962 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549962
Low power scheme for power down in integrated dual rail SRAMs Dec 13, 2021 Issued
Array ( [id] => 18607866 [patent_doc_number] => 11749342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Passive compensation for electrical distance [patent_app_type] => utility [patent_app_number] => 17/549390 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549390
Passive compensation for electrical distance Dec 12, 2021 Issued
Array ( [id] => 18080739 [patent_doc_number] => 20220406351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/643499 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643499
Semiconductor memory device for reducing effect of leakage current Dec 8, 2021 Issued
Array ( [id] => 18281144 [patent_doc_number] => 20230096616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => STORAGE DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/542427 [patent_app_country] => US [patent_app_date] => 2021-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542427
Storage device and manufacturing method thereof Dec 4, 2021 Issued
Array ( [id] => 18828909 [patent_doc_number] => 11844210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Storage device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/542429 [patent_app_country] => US [patent_app_date] => 2021-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542429
Storage device and manufacturing method thereof Dec 4, 2021 Issued
Array ( [id] => 19444256 [patent_doc_number] => 12094542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Device and method to generate bias voltages in non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/542323 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7794 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542323
Device and method to generate bias voltages in non-volatile memory Dec 2, 2021 Issued
Array ( [id] => 17630312 [patent_doc_number] => 20220165327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => INTERFACE OF A MEMORY CIRCUIT AND MEMORY SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 17/529709 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529709 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529709
Interface of a memory circuit and memory system thereof Nov 17, 2021 Issued
Array ( [id] => 17795293 [patent_doc_number] => 20220254385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => POWER RAMPING SEQUENCE CONTROL FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/522556 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522556
Power ramping sequence control for a memory device Nov 8, 2021 Issued
Array ( [id] => 18346327 [patent_doc_number] => 20230134437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => TWO-TERMINAL ONE-TIME PROGRAMMABLE FUSES FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/518937 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518937
Two-terminal one-time programmable fuses for memory cells Nov 3, 2021 Issued
Array ( [id] => 17551329 [patent_doc_number] => 20220122671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => METHOD FOR PROGRAMMING CHARGE TRAP FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/506036 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506036 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506036
Method for programming charge trap flash memory Oct 19, 2021 Issued
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