Search

Angela J Lee

Examiner (ID: 10714, Phone: (571)272-4453 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2911
Total Applications
4543
Issued Applications
4500
Pending Applications
13
Abandoned Applications
25

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18357664 [patent_doc_number] => 11646070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Memory cell sensing using an averaged reference voltage [patent_app_type] => utility [patent_app_number] => 17/499492 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15785 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499492
Memory cell sensing using an averaged reference voltage Oct 11, 2021 Issued
Array ( [id] => 18623548 [patent_doc_number] => 11756601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Differential sensing for a memory device [patent_app_type] => utility [patent_app_number] => 17/499322 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 19887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499322
Differential sensing for a memory device Oct 11, 2021 Issued
Array ( [id] => 17359634 [patent_doc_number] => 20220020430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => MEMORY OPERATION WITH DOUBLE-SIDED ASYMMETRIC DECODERS [patent_app_type] => utility [patent_app_number] => 17/491070 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491070
Memory operation with double-sided asymmetric decoders Sep 29, 2021 Issued
Array ( [id] => 18639256 [patent_doc_number] => 11763872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => 3D memory array clusters and resulting memory architecture [patent_app_type] => utility [patent_app_number] => 17/488148 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3899 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488148 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488148
3D memory array clusters and resulting memory architecture Sep 27, 2021 Issued
Array ( [id] => 18088381 [patent_doc_number] => 11538520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Negative-capacitance ferroelectric transistor assisted resistive memory programming [patent_app_type] => utility [patent_app_number] => 17/482491 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 8850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482491
Negative-capacitance ferroelectric transistor assisted resistive memory programming Sep 22, 2021 Issued
Array ( [id] => 17339213 [patent_doc_number] => 20220005544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => REPAIR CIRCUIT, MEMORY, AND REPAIR METHOD [patent_app_type] => utility [patent_app_number] => 17/477769 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477769
Repair circuit, memory, and repair method Sep 16, 2021 Issued
Array ( [id] => 17886162 [patent_doc_number] => 20220301639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR CIRCUIT, RECEIVING DEVICE, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/473269 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473269 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473269
Semiconductor circuit, receiving device, and memory system Sep 12, 2021 Issued
Array ( [id] => 18528520 [patent_doc_number] => 11715518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Dynamic inhibit voltage to reduce write power for random-access memory [patent_app_type] => utility [patent_app_number] => 17/470849 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8049 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470849
Dynamic inhibit voltage to reduce write power for random-access memory Sep 8, 2021 Issued
Array ( [id] => 18088368 [patent_doc_number] => 11538507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Header circuit placement in memory device [patent_app_type] => utility [patent_app_number] => 17/461210 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461210
Header circuit placement in memory device Aug 29, 2021 Issued
Array ( [id] => 17870459 [patent_doc_number] => 20220293196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => FREQUENCY-VOLTAGE CONVERSION CIRCUIT, SEMICONDUCTOR DEVICE, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/459499 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459499 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459499
Frequency-voltage conversion circuit, semiconductor device, and memory system Aug 26, 2021 Issued
Array ( [id] => 17447890 [patent_doc_number] => 20220068395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/407903 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407903
Memory device Aug 19, 2021 Issued
Array ( [id] => 17447863 [patent_doc_number] => 20220068368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => DEVICES AND METHODS FOR ADAPTIVE RETENTION VOLTAGE IN VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/405240 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405240 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405240
Devices and methods for adaptive retention voltage in volatile memory Aug 17, 2021 Issued
Array ( [id] => 18857056 [patent_doc_number] => 11854647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Voltage level shifter transition time reduction [patent_app_type] => utility [patent_app_number] => 17/388359 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12071 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388359
Voltage level shifter transition time reduction Jul 28, 2021 Issued
Array ( [id] => 17691833 [patent_doc_number] => 20220199126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => RECEIVERS FOR PERFORMING REFERENCE VOLTAGE TRAINING AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/377654 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377654
Receivers for performing reference voltage training and memory systems including the same Jul 15, 2021 Issued
Array ( [id] => 18415832 [patent_doc_number] => 11670377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Page buffer and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/375206 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 33 [patent_no_of_words] => 10117 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375206
Page buffer and memory device including the same Jul 13, 2021 Issued
Array ( [id] => 17339194 [patent_doc_number] => 20220005525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => Two-Bit Memory Cell and Circuit Structure Calculated in Memory Thereof [patent_app_type] => utility [patent_app_number] => 17/365841 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 498 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365841
Two-bit memory cell and circuit structure calculated in memory thereof Jun 30, 2021 Issued
Array ( [id] => 18578713 [patent_doc_number] => 11735252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Multi-level cell programming using optimized multiphase mapping with balanced gray code [patent_app_type] => utility [patent_app_number] => 17/359344 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9347 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359344
Multi-level cell programming using optimized multiphase mapping with balanced gray code Jun 24, 2021 Issued
Array ( [id] => 19007486 [patent_doc_number] => 20240071557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => FAILURE ANALYSIS METHOD, COMPUTER EQUIPMENT, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/607395 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17607395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/607395
FAILURE ANALYSIS METHOD, COMPUTER EQUIPMENT, AND STORAGE MEDIUM Jun 22, 2021 Pending
Array ( [id] => 17508786 [patent_doc_number] => 20220101889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => METHOD OF RESETTING STORAGE DEVICE, STORAGE DEVICE PERFORMING THE SAME AND DATA CENTER INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/346212 [patent_app_country] => US [patent_app_date] => 2021-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346212 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346212
Method of resetting storage device, storage device performing the same and data center including the same Jun 11, 2021 Issued
Array ( [id] => 18480996 [patent_doc_number] => 11694747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Self-selecting memory cells configured to store more than one bit per memory cell [patent_app_type] => utility [patent_app_number] => 17/337806 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 13112 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337806
Self-selecting memory cells configured to store more than one bit per memory cell Jun 2, 2021 Issued
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