Search

Angela J Lee

Examiner (ID: 10714, Phone: (571)272-4453 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2911
Total Applications
4543
Issued Applications
4500
Pending Applications
13
Abandoned Applications
25

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17818333 [patent_doc_number] => 11423954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Semiconductor memory device capable of supporting asynchronous power-down mode, and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/189501 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4377 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189501
Semiconductor memory device capable of supporting asynchronous power-down mode, and operating method thereof Mar 1, 2021 Issued
Array ( [id] => 19198103 [patent_doc_number] => 11995341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Read/write switching circuit and memory [patent_app_type] => utility [patent_app_number] => 17/595721 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9278 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17595721 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/595721
Read/write switching circuit and memory Feb 28, 2021 Issued
Array ( [id] => 18105298 [patent_doc_number] => 11545192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => System and method of power management in memory design [patent_app_type] => utility [patent_app_number] => 17/185030 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185030
System and method of power management in memory design Feb 24, 2021 Issued
Array ( [id] => 17716411 [patent_doc_number] => 11380409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Duty adjustment circuit, semiconductor storage device, and memory system [patent_app_type] => utility [patent_app_number] => 17/184849 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 21127 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184849
Duty adjustment circuit, semiconductor storage device, and memory system Feb 24, 2021 Issued
Array ( [id] => 17099955 [patent_doc_number] => 20210287746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => MEMORY CELL ARRAY OF MULTI-TIME PROGRAMMABLE NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/183528 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183528
Memory cell array of multi-time programmable non-volatile memory Feb 23, 2021 Issued
Array ( [id] => 17716400 [patent_doc_number] => 11380398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Storage device and the read operating method thereof [patent_app_type] => utility [patent_app_number] => 17/182556 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182556
Storage device and the read operating method thereof Feb 22, 2021 Issued
Array ( [id] => 18431429 [patent_doc_number] => 11676656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Memory architecture with DC biasing [patent_app_type] => utility [patent_app_number] => 17/168428 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5984 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168428
Memory architecture with DC biasing Feb 4, 2021 Issued
Array ( [id] => 17893053 [patent_doc_number] => 11456032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Systems and methods for memory cell accesses [patent_app_type] => utility [patent_app_number] => 17/162031 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10243 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162031 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162031
Systems and methods for memory cell accesses Jan 28, 2021 Issued
Array ( [id] => 16995162 [patent_doc_number] => 20210233582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => BIT-LINE VOLTAGE GENERATION CIRCUIT FOR A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING METHOD [patent_app_type] => utility [patent_app_number] => 17/159381 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159381
Bit-line voltage generation circuit for a non-volatile memory device and corresponding method Jan 26, 2021 Issued
Array ( [id] => 17477058 [patent_doc_number] => 20220084562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => SEMICONDUCTOR DEVICE FOR STABLE CONTROL OF POWER-DOWN MODE [patent_app_type] => utility [patent_app_number] => 17/150745 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150745
Semiconductor device for stable control of power-down mode Jan 14, 2021 Issued
Array ( [id] => 17373380 [patent_doc_number] => 20220028432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/148201 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148201
Semiconductor apparatus and semiconductor memory apparatus Jan 12, 2021 Issued
Array ( [id] => 18181030 [patent_doc_number] => 20230041759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => FERROELECTRIC MEMORY CIRCUIT AND READING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/791795 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17791795 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/791795
FERROELECTRIC MEMORY CIRCUIT AND READING METHOD THEREOF Jan 7, 2021 Pending
Array ( [id] => 17925675 [patent_doc_number] => 11468934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Access line disturbance mitigation [patent_app_type] => utility [patent_app_number] => 17/143728 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 21373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143728
Access line disturbance mitigation Jan 6, 2021 Issued
Array ( [id] => 17574228 [patent_doc_number] => 11322503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Integrated circuit including at least one memory cell with an antifuse device [patent_app_type] => utility [patent_app_number] => 17/141498 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4288 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141498 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141498
Integrated circuit including at least one memory cell with an antifuse device Jan 4, 2021 Issued
Array ( [id] => 17516628 [patent_doc_number] => 11295787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Reducing SRAM leakage using scalable switched capacitor regulators [patent_app_type] => utility [patent_app_number] => 17/134765 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134765
Reducing SRAM leakage using scalable switched capacitor regulators Dec 27, 2020 Issued
Array ( [id] => 18212172 [patent_doc_number] => 20230058436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SENSE AMPLIFIER, MEMORY AND METHOD FOR CONTROLLING SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/441780 [patent_app_country] => US [patent_app_date] => 2020-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17441780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/441780
Sense amplifier, memory and method for controlling sense amplifier Dec 24, 2020 Issued
Array ( [id] => 16765293 [patent_doc_number] => 20210110875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/131400 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131400
Memory system Dec 21, 2020 Issued
Array ( [id] => 17924493 [patent_doc_number] => 11467741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Dynamic peak power management for multi-die operations [patent_app_type] => utility [patent_app_number] => 17/127405 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127405 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127405
Dynamic peak power management for multi-die operations Dec 17, 2020 Issued
Array ( [id] => 17010663 [patent_doc_number] => 20210241824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SHARED POWER FOOTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/119357 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119357
Shared power footer circuit Dec 10, 2020 Issued
Array ( [id] => 16780768 [patent_doc_number] => 20210117847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => CONSTRUCTING AND PROGRAMMING QUANTUM HARDWARE FOR ROBUST QUANTUM ANNEALING PROCESSES [patent_app_type] => utility [patent_app_number] => 17/115493 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115493
Constructing and programming quantum hardware for robust quantum annealing processes Dec 7, 2020 Issued
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