Search

Angela R. Holmes

Examiner (ID: 13286, Phone: (571)270-3357 , Office: P/2497 )

Most Active Art Unit
2497
Art Unit(s)
2497, 2498, 2438
Total Applications
433
Issued Applications
374
Pending Applications
1
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17217905 [patent_doc_number] => 20210351243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => DISPLAY DEVICES, DISPLAY PANELS AND TRANSPARENT DISPLAY PANELS THEREOF [patent_app_type] => utility [patent_app_number] => 17/381569 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381569
Display devices, display panels and transparent display panels thereof Jul 20, 2021 Issued
Array ( [id] => 20334531 [patent_doc_number] => 12464827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Resistor with exponential-weighted trim [patent_app_type] => utility [patent_app_number] => 17/376747 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376747
Resistor with exponential-weighted trim Jul 14, 2021 Issued
Array ( [id] => 20390738 [patent_doc_number] => 12490486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Compound semiconductor substrate and method for manufacturing compound semiconductor substrate [patent_app_type] => utility [patent_app_number] => 18/016177 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 9830 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18016177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/016177
Compound semiconductor substrate and method for manufacturing compound semiconductor substrate Jul 12, 2021 Issued
Array ( [id] => 19294691 [patent_doc_number] => 12034056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Semiconductor devices including gate structures with gate spacers [patent_app_type] => utility [patent_app_number] => 17/371907 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/371907
Semiconductor devices including gate structures with gate spacers Jul 8, 2021 Issued
Array ( [id] => 20332771 [patent_doc_number] => 12463055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Package substrate manufacturing method [patent_app_type] => utility [patent_app_number] => 18/005608 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18005608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/005608
Package substrate manufacturing method Jul 8, 2021 Issued
Array ( [id] => 18190797 [patent_doc_number] => 11581401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Pin diode including a conductive layer, and fabrication process [patent_app_type] => utility [patent_app_number] => 17/370397 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370397
Pin diode including a conductive layer, and fabrication process Jul 7, 2021 Issued
Array ( [id] => 18124133 [patent_doc_number] => 20230009745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SEMICONDUCTOR DEVICE, AND METHOD FOR PROTECTING LOW-K DIELECTRIC FEATURE OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/370265 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370265
Semiconductor device, and method for protecting low-k dielectric feature of semiconductor device Jul 7, 2021 Issued
Array ( [id] => 18357901 [patent_doc_number] => 11646308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Through silicon via design for stacking integrated circuits [patent_app_type] => utility [patent_app_number] => 17/370045 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 7350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370045 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370045
Through silicon via design for stacking integrated circuits Jul 7, 2021 Issued
Array ( [id] => 17339375 [patent_doc_number] => 20220005706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH DIFFERENT NON-SEMICONDUCTOR THERMAL STABILITIES [patent_app_type] => utility [patent_app_number] => 17/305192 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305192
Method for making a semiconductor superlattices with different non-semiconductor thermal stabilities Jun 30, 2021 Issued
Array ( [id] => 19428152 [patent_doc_number] => 12087585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Low-temperature implant for buried layer formation [patent_app_type] => utility [patent_app_number] => 17/362946 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2662 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362946 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362946
Low-temperature implant for buried layer formation Jun 28, 2021 Issued
Array ( [id] => 18081103 [patent_doc_number] => 20220406715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => STACKED FET INTEGRATION WITH BSPDN [patent_app_type] => utility [patent_app_number] => 17/304460 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304460
Stacked FET integration with BSPDN Jun 21, 2021 Issued
Array ( [id] => 17145381 [patent_doc_number] => 20210313394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/353521 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353521
Semiconductor structure and manufacturing method of the same Jun 20, 2021 Issued
Array ( [id] => 17583243 [patent_doc_number] => 20220140098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => Nano Transistors with Source/Drain Having Side Contacts to 2-D Material [patent_app_type] => utility [patent_app_number] => 17/351622 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351622
Nano transistors with source/drain having side contacts to 2-D material Jun 17, 2021 Issued
Array ( [id] => 17145312 [patent_doc_number] => 20210313325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => METAL GATE MODULATION TO IMPROVE KINK EFFECT [patent_app_type] => utility [patent_app_number] => 17/351392 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351392 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351392
Metal gate modulation to improve kink effect Jun 17, 2021 Issued
Array ( [id] => 18190825 [patent_doc_number] => 11581429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Power semiconductor switch having a cross-trench structure [patent_app_type] => utility [patent_app_number] => 17/350505 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350505
Power semiconductor switch having a cross-trench structure Jun 16, 2021 Issued
Array ( [id] => 18190825 [patent_doc_number] => 11581429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Power semiconductor switch having a cross-trench structure [patent_app_type] => utility [patent_app_number] => 17/350505 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350505
Power semiconductor switch having a cross-trench structure Jun 16, 2021 Issued
Array ( [id] => 18190825 [patent_doc_number] => 11581429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Power semiconductor switch having a cross-trench structure [patent_app_type] => utility [patent_app_number] => 17/350505 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350505
Power semiconductor switch having a cross-trench structure Jun 16, 2021 Issued
Array ( [id] => 18190825 [patent_doc_number] => 11581429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Power semiconductor switch having a cross-trench structure [patent_app_type] => utility [patent_app_number] => 17/350505 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350505
Power semiconductor switch having a cross-trench structure Jun 16, 2021 Issued
Array ( [id] => 19935120 [patent_doc_number] => 12308328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Semiconductor memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/345184 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 1299 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345184
Semiconductor memory device and method for manufacturing the same Jun 10, 2021 Issued
Array ( [id] => 18654644 [patent_doc_number] => 20230300492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => METHOD FOR MANUFACTURING LIGHT DETECTION DEVICE, LIGHT DETECTION DEVICE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/999845 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17999845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/999845
Method for manufacturing light detection device, light detection device, and electronic device Jun 2, 2021 Issued
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