Search

Angela R. Holmes

Examiner (ID: 13286, Phone: (571)270-3357 , Office: P/2497 )

Most Active Art Unit
2497
Art Unit(s)
2497, 2498, 2438
Total Applications
433
Issued Applications
374
Pending Applications
1
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17070763 [patent_doc_number] => 20210272980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/007871 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007871
Semiconductor storage device and manufacturing method thereof Aug 30, 2020 Issued
Array ( [id] => 17652761 [patent_doc_number] => 11355501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Method for manufacturing static random access memory device [patent_app_type] => utility [patent_app_number] => 17/005770 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 47 [patent_no_of_words] => 8417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/005770
Method for manufacturing static random access memory device Aug 27, 2020 Issued
Array ( [id] => 18494242 [patent_doc_number] => 11699663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Passivation scheme design for wafer singulation [patent_app_type] => utility [patent_app_number] => 17/006365 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006365
Passivation scheme design for wafer singulation Aug 27, 2020 Issued
Array ( [id] => 19926211 [patent_doc_number] => 12300504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Film processing method and semiconductor device manufacturing method [patent_app_type] => utility [patent_app_number] => 17/005568 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 1179 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/005568
Film processing method and semiconductor device manufacturing method Aug 27, 2020 Issued
Array ( [id] => 16920551 [patent_doc_number] => 20210193643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SEMICONDUCTOR DEVICE HAVING IMPROVED ELECTROSTATIC DISCHARGE PROTECTION [patent_app_type] => utility [patent_app_number] => 17/004396 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004396
Semiconductor device having improved electrostatic discharge protection Aug 26, 2020 Issued
Array ( [id] => 17700132 [patent_doc_number] => 11373865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Method for manufacturing semiconductor device having a film with layers of different concentrations of elements [patent_app_type] => utility [patent_app_number] => 17/004216 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4715 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004216 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004216
Method for manufacturing semiconductor device having a film with layers of different concentrations of elements Aug 26, 2020 Issued
Array ( [id] => 16660951 [patent_doc_number] => 20210057588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => MEMRISTOR WITH TWO-DIMENSIONAL (2D) MATERIAL HETEROJUNCTION AND PREPARATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/999570 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999570 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999570
MEMRISTOR WITH TWO-DIMENSIONAL (2D) MATERIAL HETEROJUNCTION AND PREPARATION METHOD THEREOF Aug 20, 2020 Abandoned
Array ( [id] => 16487681 [patent_doc_number] => 20200381290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => Integrated Memory, Integrated Assemblies, and Methods of Forming Memory Arrays [patent_app_type] => utility [patent_app_number] => 16/995529 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995529 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995529
Methods of forming integrated assemblies Aug 16, 2020 Issued
Array ( [id] => 16774061 [patent_doc_number] => 10985182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Methods for forming three-dimensional memory device without conductor residual caused by dishing [patent_app_type] => utility [patent_app_number] => 16/994503 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994503
Methods for forming three-dimensional memory device without conductor residual caused by dishing Aug 13, 2020 Issued
Array ( [id] => 17493427 [patent_doc_number] => 11282740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Bulk semiconductor structure with a multi-level polycrystalline semiconductor region and method [patent_app_type] => utility [patent_app_number] => 16/992165 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/992165
Bulk semiconductor structure with a multi-level polycrystalline semiconductor region and method Aug 12, 2020 Issued
Array ( [id] => 18120767 [patent_doc_number] => 11552166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Semiconductor device comprising resurf isolation structure surrounding an outer periphery of a high side circuit region and isolating the high side circuit region from a low side circuit region [patent_app_type] => utility [patent_app_number] => 16/989021 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 6159 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989021 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989021
Semiconductor device comprising resurf isolation structure surrounding an outer periphery of a high side circuit region and isolating the high side circuit region from a low side circuit region Aug 9, 2020 Issued
Array ( [id] => 16715805 [patent_doc_number] => 20210082952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/989168 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989168
Semiconductor device and manufacturing method thereof Aug 9, 2020 Issued
Array ( [id] => 16928461 [patent_doc_number] => 11049953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Nanosheet transistor [patent_app_type] => utility [patent_app_number] => 16/939415 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6758 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939415
Nanosheet transistor Jul 26, 2020 Issued
Array ( [id] => 20389334 [patent_doc_number] => 12489069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => High frequency package [patent_app_type] => utility [patent_app_number] => 17/765103 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17765103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/765103
High frequency package Jul 19, 2020 Issued
Array ( [id] => 17047959 [patent_doc_number] => 11101149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Semiconductor fabrication with electrochemical apparatus [patent_app_type] => utility [patent_app_number] => 16/933727 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 66 [patent_no_of_words] => 7849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933727
Semiconductor fabrication with electrochemical apparatus Jul 19, 2020 Issued
Array ( [id] => 16731404 [patent_doc_number] => 20210098552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/928575 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928575 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928575
Display apparatus Jul 13, 2020 Issued
Array ( [id] => 17780289 [patent_doc_number] => 20220246639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => 3-DIMENSIONAL NAND MEMORY WITH REDUCED THERMAL BUDGET [patent_app_type] => utility [patent_app_number] => 17/626446 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/626446
3-dimensional NAND memory with reduced thermal budget Jul 12, 2020 Issued
Array ( [id] => 18464399 [patent_doc_number] => 11688694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Secure chips with serial numbers [patent_app_type] => utility [patent_app_number] => 16/927805 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 14776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927805
Secure chips with serial numbers Jul 12, 2020 Issued
Array ( [id] => 16846029 [patent_doc_number] => 11018125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Multi-chip package with offset 3D structure [patent_app_type] => utility [patent_app_number] => 16/927111 [patent_app_country] => US [patent_app_date] => 2020-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4689 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16927111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/927111
Multi-chip package with offset 3D structure Jul 12, 2020 Issued
Array ( [id] => 16394658 [patent_doc_number] => 20200335599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => Field Effect Transistors with Ferroelectric Dieletric Materials [patent_app_type] => utility [patent_app_number] => 16/946736 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16946736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/946736
Field effect transistors with ferroelectric dielectric materials Jul 1, 2020 Issued
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