Search

Angela R. Holmes

Examiner (ID: 13286, Phone: (571)270-3357 , Office: P/2497 )

Most Active Art Unit
2497
Art Unit(s)
2497, 2498, 2438
Total Applications
433
Issued Applications
374
Pending Applications
1
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15299841 [patent_doc_number] => 20190393056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 16/563466 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563466 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563466
Substrate processing apparatus, method of manufacturing semiconductor device, and recording medium Sep 5, 2019 Issued
Array ( [id] => 16645526 [patent_doc_number] => 10923392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Interconnect structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/562207 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9476 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562207 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562207
Interconnect structure and method of forming the same Sep 4, 2019 Issued
Array ( [id] => 15332523 [patent_doc_number] => 20200006591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => CONDUCTIVE ISOLATION BETWEEN PHOTOTRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/558957 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558957 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558957
Conductive isolation between phototransistors Sep 2, 2019 Issued
Array ( [id] => 17787716 [patent_doc_number] => 11410850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Aluminum oxide semiconductor manufacturing method and aluminum oxide semiconductor manufacturing device [patent_app_type] => utility [patent_app_number] => 17/272869 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 15807 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17272869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/272869
Aluminum oxide semiconductor manufacturing method and aluminum oxide semiconductor manufacturing device Aug 29, 2019 Issued
Array ( [id] => 16495899 [patent_doc_number] => 10861951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Transistor layout to reduce kink effect [patent_app_type] => utility [patent_app_number] => 16/550497 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 8288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550497
Transistor layout to reduce kink effect Aug 25, 2019 Issued
Array ( [id] => 15260117 [patent_doc_number] => 20190378792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => SWITCHING DEVICE [patent_app_type] => utility [patent_app_number] => 16/549376 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549376
Switching device Aug 22, 2019 Issued
Array ( [id] => 16660710 [patent_doc_number] => 20210057347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/547611 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547611 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547611
Semiconductor package and manufacturing method thereof Aug 21, 2019 Issued
Array ( [id] => 17032963 [patent_doc_number] => 11094783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Semiconductor device having a silicon oxide film with a gradual downward inclination and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/547628 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 7750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547628
Semiconductor device having a silicon oxide film with a gradual downward inclination and method of manufacturing semiconductor device Aug 21, 2019 Issued
Array ( [id] => 15598077 [patent_doc_number] => 20200075573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => RESISTOR WITH EXPONENTIAL-WEIGHTED TRIM [patent_app_type] => utility [patent_app_number] => 16/547615 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547615
Resistor with exponential-weighted trim Aug 21, 2019 Issued
Array ( [id] => 17590880 [patent_doc_number] => 11329157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Two-terminal biristor with polysilicon emitter layer and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/607410 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7030 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16607410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/607410
Two-terminal biristor with polysilicon emitter layer and method of manufacturing the same Aug 19, 2019 Issued
Array ( [id] => 15260391 [patent_doc_number] => 20190378929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => CHARGE CARRIER TRANSPORT FACILITATED BY STRAIN [patent_app_type] => utility [patent_app_number] => 16/543957 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543957 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543957
CHARGE CARRIER TRANSPORT FACILITATED BY STRAIN Aug 18, 2019 Abandoned
Array ( [id] => 16348220 [patent_doc_number] => 20200312871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/541142 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541142
Three-dimensional memory devices and fabrication methods thereof Aug 13, 2019 Issued
Array ( [id] => 17002673 [patent_doc_number] => 11081496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Three-dimensional memory devices and fabrication methods thereof [patent_app_type] => utility [patent_app_number] => 16/541141 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 59 [patent_no_of_words] => 17964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541141
Three-dimensional memory devices and fabrication methods thereof Aug 13, 2019 Issued
Array ( [id] => 16495720 [patent_doc_number] => 10861769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Insulated heat dissipation substrate [patent_app_type] => utility [patent_app_number] => 16/540321 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7739 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540321 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540321
Insulated heat dissipation substrate Aug 13, 2019 Issued
Array ( [id] => 16738906 [patent_doc_number] => 10964570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Semiconductor wafer storage system and method of supplying fluid for semiconductor wafer storage [patent_app_type] => utility [patent_app_number] => 16/529082 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5901 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529082
Semiconductor wafer storage system and method of supplying fluid for semiconductor wafer storage Jul 31, 2019 Issued
Array ( [id] => 15656805 [patent_doc_number] => 20200090933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 16/527326 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527326 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527326
CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAME Jul 30, 2019 Abandoned
Array ( [id] => 15154195 [patent_doc_number] => 20190355575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/528048 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528048
Method of manufacturing semiconductor device Jul 30, 2019 Issued
Array ( [id] => 15154739 [patent_doc_number] => 20190355847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => STRUCTURE OF TRENCH METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/526588 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526588
STRUCTURE OF TRENCH METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR Jul 29, 2019 Abandoned
Array ( [id] => 16536732 [patent_doc_number] => 10879347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Capacitor [patent_app_type] => utility [patent_app_number] => 16/522045 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8953 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522045
Capacitor Jul 24, 2019 Issued
Array ( [id] => 17032868 [patent_doc_number] => 11094686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Integrated circuit including multi-height standard cell and method of designing the same [patent_app_type] => utility [patent_app_number] => 16/521845 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 12297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521845 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521845
Integrated circuit including multi-height standard cell and method of designing the same Jul 24, 2019 Issued
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