Search

Angela R. Holmes

Examiner (ID: 13286, Phone: (571)270-3357 , Office: P/2497 )

Most Active Art Unit
2497
Art Unit(s)
2497, 2498, 2438
Total Applications
433
Issued Applications
374
Pending Applications
1
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18789656 [patent_doc_number] => 20230378365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MULTI-GATE DEVICE AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/366392 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366392
Multi-gate device and related methods Aug 6, 2023 Issued
Array ( [id] => 19639706 [patent_doc_number] => 12170323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Nano transistors with source/drain having side contacts to 2-D material [patent_app_type] => utility [patent_app_number] => 18/365995 [patent_app_country] => US [patent_app_date] => 2023-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 33 [patent_no_of_words] => 7228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365995 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365995
Nano transistors with source/drain having side contacts to 2-D material Aug 5, 2023 Issued
Array ( [id] => 18789297 [patent_doc_number] => 20230377948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => METHOD FOR FORMING A SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/365402 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365402
Method for forming a semiconductor-on-insulator (SOI) substrate Aug 3, 2023 Issued
Array ( [id] => 18812590 [patent_doc_number] => 20230386927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Local Gate Height Tuning by CMP and Dummy Gate Design [patent_app_type] => utility [patent_app_number] => 18/365405 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365405
Local gate height tuning by CMP and dummy gate design Aug 3, 2023 Issued
Array ( [id] => 18789548 [patent_doc_number] => 20230378234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => IMAGE SENSOR DEVICE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/365680 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365680 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365680
Image sensor device and methods of forming the same Aug 3, 2023 Issued
Array ( [id] => 19720345 [patent_doc_number] => 12205888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Semiconductor packages and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/363692 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363692 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363692
Semiconductor packages and methods of forming the same Jul 31, 2023 Issued
Array ( [id] => 18789237 [patent_doc_number] => 20230377881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => STRAIN RELIEF TRENCHES FOR EPITAXIAL GROWTH [patent_app_type] => utility [patent_app_number] => 18/362240 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362240 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362240
STRAIN RELIEF TRENCHES FOR EPITAXIAL GROWTH Jul 30, 2023 Pending
Array ( [id] => 19751675 [patent_doc_number] => 20250040240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => STACKED FIELD EFFECT TRANSISTOR HYBRID GATE CUT [patent_app_type] => utility [patent_app_number] => 18/361255 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361255
STACKED FIELD EFFECT TRANSISTOR HYBRID GATE CUT Jul 27, 2023 Pending
Array ( [id] => 19926431 [patent_doc_number] => 12300727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Process and structure for source/drain contacts [patent_app_type] => utility [patent_app_number] => 18/361262 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 3270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361262 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361262
Process and structure for source/drain contacts Jul 27, 2023 Issued
Array ( [id] => 19828786 [patent_doc_number] => 12249580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Passivation scheme design for wafer singulation [patent_app_type] => utility [patent_app_number] => 18/358530 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358530
Passivation scheme design for wafer singulation Jul 24, 2023 Issued
Array ( [id] => 18906250 [patent_doc_number] => 20240021735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SEMICONDUCTOR CHIP [patent_app_type] => utility [patent_app_number] => 18/358689 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358689 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358689
Semiconductor chip Jul 24, 2023 Issued
Array ( [id] => 18774215 [patent_doc_number] => 20230369046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 18/225994 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225994
CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAME Jul 24, 2023 Abandoned
Array ( [id] => 20416794 [patent_doc_number] => 12500087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Semiconductor structure with air gap in pattern-dense region and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/220963 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 7007 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220963 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220963
Semiconductor structure with air gap in pattern-dense region and method of manufacturing the same Jul 11, 2023 Issued
Array ( [id] => 18759680 [patent_doc_number] => 20230363169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => HYBRID BONDING CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/221358 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221358
Hybrid bonding contact structure of three-dimensional memory device Jul 11, 2023 Issued
Array ( [id] => 19733923 [patent_doc_number] => 12211925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Gate-all-around integrated circuit structures having oxide sub-fins [patent_app_type] => utility [patent_app_number] => 18/219986 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 14148 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219986
Gate-all-around integrated circuit structures having oxide sub-fins Jul 9, 2023 Issued
Array ( [id] => 18745653 [patent_doc_number] => 20230354647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/347778 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347778
Display device Jul 5, 2023 Issued
Array ( [id] => 19057051 [patent_doc_number] => 20240099020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/345266 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345266
MEMORY DEVICE Jun 29, 2023 Pending
Array ( [id] => 19662055 [patent_doc_number] => 20240429120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => Topside Cooling for Semiconductor Device [patent_app_type] => utility [patent_app_number] => 18/340503 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340503 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340503
Topside Cooling for Semiconductor Device Jun 22, 2023 Pending
Array ( [id] => 19646477 [patent_doc_number] => 20240420997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SELECTIVE LINER DEPOSITION FOR VIA RESISTANCE REDUCTION [patent_app_type] => utility [patent_app_number] => 18/211502 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211502 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211502
SELECTIVE LINER DEPOSITION FOR VIA RESISTANCE REDUCTION Jun 18, 2023 Pending
Array ( [id] => 19275787 [patent_doc_number] => 12025914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Silver patterning and interconnect processes [patent_app_type] => utility [patent_app_number] => 18/327785 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6250 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327785
Silver patterning and interconnect processes May 31, 2023 Issued
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