Search

Angela R. Holmes

Examiner (ID: 13286, Phone: (571)270-3357 , Office: P/2497 )

Most Active Art Unit
2497
Art Unit(s)
2497, 2498, 2438
Total Applications
433
Issued Applications
374
Pending Applications
1
Abandoned Applications
61

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20246105 [patent_doc_number] => 12426451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Display apparatus including a shielding conductive layer [patent_app_type] => utility [patent_app_number] => 17/950227 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950227
Display apparatus including a shielding conductive layer Sep 21, 2022 Issued
Array ( [id] => 18146414 [patent_doc_number] => 20230020271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/949241 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949241
High electron mobility transistor and fabrication method thereof Sep 20, 2022 Issued
Array ( [id] => 19095470 [patent_doc_number] => 11956953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Joint opening structures of three-dimensional memory devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/934161 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 120 [patent_figures_cnt] => 133 [patent_no_of_words] => 26970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934161
Joint opening structures of three-dimensional memory devices and methods for forming the same Sep 20, 2022 Issued
Array ( [id] => 18140021 [patent_doc_number] => 20230013859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/947227 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/947227
Semiconductor structure and method for preparing semiconductor structure Sep 18, 2022 Issued
Array ( [id] => 20258990 [patent_doc_number] => 12431353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Hardmask structure and method of forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/946355 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7161 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946355
Hardmask structure and method of forming semiconductor structure Sep 15, 2022 Issued
Array ( [id] => 19055009 [patent_doc_number] => 20240096978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) APPARATUS WITH SELF-ALIGNED BACKSIDE CONTACT [patent_app_type] => utility [patent_app_number] => 17/946017 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946017
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) APPARATUS WITH SELF-ALIGNED BACKSIDE CONTACT Sep 14, 2022 Pending
Array ( [id] => 19054917 [patent_doc_number] => 20240096886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => HETEROGENEOUS GATE ALL AROUND DIELECTRIC THICKNESS [patent_app_type] => utility [patent_app_number] => 17/932557 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932557
Heterogeneous gate all around dielectric thickness Sep 14, 2022 Issued
Array ( [id] => 19038325 [patent_doc_number] => 20240088140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => HEIGHT CONTROL IN NANOSHEET DEVICES [patent_app_type] => utility [patent_app_number] => 17/943751 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943751
HEIGHT CONTROL IN NANOSHEET DEVICES Sep 12, 2022 Pending
Array ( [id] => 20319341 [patent_doc_number] => 12457905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features [patent_app_type] => utility [patent_app_number] => 17/943974 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943974
Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features Sep 12, 2022 Issued
Array ( [id] => 20132231 [patent_doc_number] => 12374549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Method of forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/901525 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901525
Method of forming semiconductor structure Aug 31, 2022 Issued
Array ( [id] => 19199050 [patent_doc_number] => 11996298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Reversed tone patterning method for dipole incorporation for multiple threshold voltages [patent_app_type] => utility [patent_app_number] => 17/890980 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 11387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890980
Reversed tone patterning method for dipole incorporation for multiple threshold voltages Aug 17, 2022 Issued
Array ( [id] => 18639600 [patent_doc_number] => 11764224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Semiconductor integrated circuit device [patent_app_type] => utility [patent_app_number] => 17/887913 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 8285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887913
Semiconductor integrated circuit device Aug 14, 2022 Issued
Array ( [id] => 18040079 [patent_doc_number] => 20220384296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT [patent_app_type] => utility [patent_app_number] => 17/818782 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818782
Method of making a semiconductor device having a thermal contact Aug 9, 2022 Issued
Array ( [id] => 19063184 [patent_doc_number] => 11942436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Passivation scheme design for wafer singulation [patent_app_type] => utility [patent_app_number] => 17/883932 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883932
Passivation scheme design for wafer singulation Aug 8, 2022 Issued
Array ( [id] => 18766945 [patent_doc_number] => 11817354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Local gate height tuning by cmp and dummy gate design [patent_app_type] => utility [patent_app_number] => 17/884324 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 10899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884324
Local gate height tuning by cmp and dummy gate design Aug 8, 2022 Issued
Array ( [id] => 18024563 [patent_doc_number] => 20220376062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => SEMICONDUCTOR DEVICE HAVING NEEDLE-SHAPED FIRST FIELD PLATE STRUCTURES AND NEEDLE-SHAPED SECOND FIELD PLATE STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/881842 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881842 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881842
SEMICONDUCTOR DEVICE HAVING NEEDLE-SHAPED FIRST FIELD PLATE STRUCTURES AND NEEDLE-SHAPED SECOND FIELD PLATE STRUCTURES Aug 4, 2022 Pending
Array ( [id] => 18767089 [patent_doc_number] => 11817503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/875152 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875152
Semiconductor device Jul 26, 2022 Issued
Array ( [id] => 17993236 [patent_doc_number] => 20220359273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => METHOD FOR FORMING A SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/869837 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869837
Method for forming a semiconductor-on-insulator (SOI) substrate Jul 20, 2022 Issued
Array ( [id] => 17993157 [patent_doc_number] => 20220359194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE WITH A POROUS PORTION, WAFER COMPOSITE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/869524 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869524
Semiconductor device with a porous portion, wafer composite and method of manufacturing a semiconductor device Jul 19, 2022 Issued
Array ( [id] => 18586134 [patent_doc_number] => 20230268399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => LOW CONTACT RESISTANCE UNSILICIDES FOR SEMICONDUCTOR APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/863644 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863644
LOW CONTACT RESISTANCE UNSILICIDES FOR SEMICONDUCTOR APPLICATIONS Jul 12, 2022 Abandoned
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