Angelica M Mckinney
Examiner (ID: 15529, Phone: (571)270-3321 , Office: P/2653 )
Most Active Art Unit | 2653 |
Art Unit(s) | 2653, 2694 |
Total Applications | 528 |
Issued Applications | 405 |
Pending Applications | 54 |
Abandoned Applications | 69 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17840484
[patent_doc_number] => 20220277790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => MEMORY CHIP AND METHOD OF CONTROLLING MEMORY CHIP
[patent_app_type] => utility
[patent_app_number] => 17/627989
[patent_app_country] => US
[patent_app_date] => 2020-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 38649
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17627989
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/627989 | MEMORY CHIP AND METHOD OF CONTROLLING MEMORY CHIP | Jul 20, 2020 | Pending |
Array
(
[id] => 17018167
[patent_doc_number] => 11087812
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-08-10
[patent_title] => Magnetoresistive random-access memory
[patent_app_type] => utility
[patent_app_number] => 16/931438
[patent_app_country] => US
[patent_app_date] => 2020-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 3669
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931438
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/931438 | Magnetoresistive random-access memory | Jul 15, 2020 | Issued |
Array
(
[id] => 17040382
[patent_doc_number] => 20210257018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-19
[patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/922683
[patent_app_country] => US
[patent_app_date] => 2020-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7394
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922683
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/922683 | Memory device and method of operating the same | Jul 6, 2020 | Issued |
Array
(
[id] => 17047816
[patent_doc_number] => 11101006
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-24
[patent_title] => Read level tracking and optimization
[patent_app_type] => utility
[patent_app_number] => 16/921804
[patent_app_country] => US
[patent_app_date] => 2020-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 12418
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921804
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/921804 | Read level tracking and optimization | Jul 5, 2020 | Issued |
Array
(
[id] => 17667175
[patent_doc_number] => 11360874
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-14
[patent_title] => Registering clock driver controlled decision feedback equalizer training process
[patent_app_type] => utility
[patent_app_number] => 16/919649
[patent_app_country] => US
[patent_app_date] => 2020-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5647
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919649
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/919649 | Registering clock driver controlled decision feedback equalizer training process | Jul 1, 2020 | Issued |
Array
(
[id] => 17590478
[patent_doc_number] => 11328753
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-10
[patent_title] => Methods of performing self-write operation and semiconductor devices used therefor
[patent_app_type] => utility
[patent_app_number] => 16/912310
[patent_app_country] => US
[patent_app_date] => 2020-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 11504
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912310
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/912310 | Methods of performing self-write operation and semiconductor devices used therefor | Jun 24, 2020 | Issued |
Array
(
[id] => 17764559
[patent_doc_number] => 20220238172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => Mechanical memory and tunable nano-electromechanical systems (NEMS) resonator
[patent_app_type] => utility
[patent_app_number] => 17/613192
[patent_app_country] => US
[patent_app_date] => 2020-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7462
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17613192
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/613192 | Mechanical memory and tunable nano-electromechanical systems (NEMS) resonator | May 26, 2020 | Issued |
Array
(
[id] => 17737731
[patent_doc_number] => 20220223193
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => METHOD AND APPARATUS FOR IMPROVING SYSTEM DRAM RELIABILITY, AND STORAGE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 17/610718
[patent_app_country] => US
[patent_app_date] => 2020-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5962
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17610718
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/610718 | Method and apparatus for improving system DRAM reliability, and storage medium | May 18, 2020 | Issued |
Array
(
[id] => 17210490
[patent_doc_number] => 11170865
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-11-09
[patent_title] => Area-efficient dynamic memory redundancy scheme with priority decoding
[patent_app_type] => utility
[patent_app_number] => 16/868402
[patent_app_country] => US
[patent_app_date] => 2020-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7737
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868402
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/868402 | Area-efficient dynamic memory redundancy scheme with priority decoding | May 5, 2020 | Issued |
Array
(
[id] => 17379967
[patent_doc_number] => 11237983
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-01
[patent_title] => Memory device, method of operating memory device, and computer system including memory device
[patent_app_type] => utility
[patent_app_number] => 16/865580
[patent_app_country] => US
[patent_app_date] => 2020-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 11273
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16865580
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/865580 | Memory device, method of operating memory device, and computer system including memory device | May 3, 2020 | Issued |
Array
(
[id] => 17500452
[patent_doc_number] => 11289162
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-29
[patent_title] => Analog content addressable memory utilizing three terminal memory devices
[patent_app_type] => utility
[patent_app_number] => 16/862997
[patent_app_country] => US
[patent_app_date] => 2020-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6809
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862997
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/862997 | Analog content addressable memory utilizing three terminal memory devices | Apr 29, 2020 | Issued |
Array
(
[id] => 17878648
[patent_doc_number] => 11450672
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation
[patent_app_type] => utility
[patent_app_number] => 16/859600
[patent_app_country] => US
[patent_app_date] => 2020-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6346
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859600
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/859600 | Ultra-deep compute static random access memory with high compute throughput and multi-directional data propagation | Apr 26, 2020 | Issued |
Array
(
[id] => 16240023
[patent_doc_number] => 20200257257
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => APPARATUS AND METHOD FOR CONTROLLING COMFORT TEMPERATURE OF AIR CONDITIONING DEVICE OR AIR CONDITIONING SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/859421
[patent_app_country] => US
[patent_app_date] => 2020-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10115
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859421
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/859421 | Apparatus and method for controlling comfort temperature of air conditioning device or air conditioning system | Apr 26, 2020 | Issued |
Array
(
[id] => 17410026
[patent_doc_number] => 11250922
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Memory cell, memory device, and related identification tag
[patent_app_type] => utility
[patent_app_number] => 16/852878
[patent_app_country] => US
[patent_app_date] => 2020-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 5795
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852878
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/852878 | Memory cell, memory device, and related identification tag | Apr 19, 2020 | Issued |
Array
(
[id] => 17558911
[patent_doc_number] => 11315630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-26
[patent_title] => Parallel port enablement in pseudo-dual-port memory designs
[patent_app_type] => utility
[patent_app_number] => 16/844501
[patent_app_country] => US
[patent_app_date] => 2020-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10240
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844501
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/844501 | Parallel port enablement in pseudo-dual-port memory designs | Apr 8, 2020 | Issued |
Array
(
[id] => 17158775
[patent_doc_number] => 20210319826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => CENTRALIZED DFE RESET GENERATOR FOR A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/844182
[patent_app_country] => US
[patent_app_date] => 2020-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6577
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844182
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/844182 | Centralized DFE reset generator for a memory device | Apr 8, 2020 | Issued |
Array
(
[id] => 16455774
[patent_doc_number] => 20200365200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-19
[patent_title] => NON-VOLATILE MEMORY AND MEMORY SECTOR THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/837623
[patent_app_country] => US
[patent_app_date] => 2020-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8320
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837623
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/837623 | Non-volatile memory and memory sector thereof | Mar 31, 2020 | Issued |
Array
(
[id] => 17181129
[patent_doc_number] => 11158378
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-26
[patent_title] => Non-volatile memory and data writing method thereof
[patent_app_type] => utility
[patent_app_number] => 16/820739
[patent_app_country] => US
[patent_app_date] => 2020-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4595
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820739
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/820739 | Non-volatile memory and data writing method thereof | Mar 16, 2020 | Issued |
Array
(
[id] => 16676985
[patent_doc_number] => 20210065751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/816476
[patent_app_country] => US
[patent_app_date] => 2020-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8041
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816476
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/816476 | Memory device | Mar 11, 2020 | Issued |
Array
(
[id] => 16845743
[patent_doc_number] => 11017837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-25
[patent_title] => Memory system
[patent_app_type] => utility
[patent_app_number] => 16/812944
[patent_app_country] => US
[patent_app_date] => 2020-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 21
[patent_no_of_words] => 13787
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812944
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/812944 | Memory system | Mar 8, 2020 | Issued |