Search

Angelica M Mckinney

Examiner (ID: 15529, Phone: (571)270-3321 , Office: P/2653 )

Most Active Art Unit
2653
Art Unit(s)
2653, 2694
Total Applications
528
Issued Applications
405
Pending Applications
54
Abandoned Applications
69

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9900194 [patent_doc_number] => 20150055393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'Semiconductor Device Having Multi-Level Wiring Structure' [patent_app_type] => utility [patent_app_number] => 14/507016 [patent_app_country] => US [patent_app_date] => 2014-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14507016 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/507016
Semiconductor Device Having Multi-Level Wiring Structure Oct 5, 2014 Abandoned
Array ( [id] => 11787331 [patent_doc_number] => 09396786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Memory and memory system including the same' [patent_app_type] => utility [patent_app_number] => 14/506366 [patent_app_country] => US [patent_app_date] => 2014-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13925 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14506366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/506366
Memory and memory system including the same Oct 2, 2014 Issued
Array ( [id] => 14263939 [patent_doc_number] => 10281529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Apparatus for measuring cell internal resistance online and measurement method therefor [patent_app_type] => utility [patent_app_number] => 14/770874 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3521 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14770874 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/770874
Apparatus for measuring cell internal resistance online and measurement method therefor Sep 25, 2014 Issued
Array ( [id] => 11020885 [patent_doc_number] => 20160217839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'HIGH CAPACITY MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/024454 [patent_app_country] => US [patent_app_date] => 2014-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21078 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15024454 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/024454
High capacity memory system Sep 23, 2014 Issued
Array ( [id] => 10966098 [patent_doc_number] => 20140369130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'LOCAL SELF-BOOST USING A PLURALITY OF CUT-OFF CELLS ON A SINGLE SIDE OF A STRING OF MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 14/475828 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475828 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475828
Local self-boost using a plurality of cut-off cells on a single side of a string of memory cells Sep 2, 2014 Issued
Array ( [id] => 11615297 [patent_doc_number] => 09653158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Light incident angle controllable electronic device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/465378 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4351 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14465378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/465378
Light incident angle controllable electronic device and manufacturing method thereof Aug 20, 2014 Issued
Array ( [id] => 10617393 [patent_doc_number] => 09336839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Integrated circuit and memory device' [patent_app_type] => utility [patent_app_number] => 14/465514 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4292 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14465514 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/465514
Integrated circuit and memory device Aug 20, 2014 Issued
Array ( [id] => 10232110 [patent_doc_number] => 20150117104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/462584 [patent_app_country] => US [patent_app_date] => 2014-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6276 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14462584 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/462584
Semiconductor memory device Aug 18, 2014 Issued
Array ( [id] => 11214544 [patent_doc_number] => 09443582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Nonvolatile memory device and method for testing nonvolatile memory device using variable resistance material' [patent_app_type] => utility [patent_app_number] => 14/463376 [patent_app_country] => US [patent_app_date] => 2014-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7897 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463376 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/463376
Nonvolatile memory device and method for testing nonvolatile memory device using variable resistance material Aug 18, 2014 Issued
Array ( [id] => 11180453 [patent_doc_number] => 09412446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'Multilevel resistive information storage and retrieval' [patent_app_type] => utility [patent_app_number] => 14/462472 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 19739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14462472 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/462472
Multilevel resistive information storage and retrieval Aug 17, 2014 Issued
Array ( [id] => 9907809 [patent_doc_number] => 20150063010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING FOR STATIC RANDOM ACCESS MEMORY (SRAM)' [patent_app_type] => utility [patent_app_number] => 14/461338 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14461338 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/461338
NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING FOR STATIC RANDOM ACCESS MEMORY (SRAM) Aug 14, 2014 Abandoned
Array ( [id] => 9894349 [patent_doc_number] => 20150049548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'Read Methods for Non-Volatile Memory Devices and Related Non-Volatile Memory Devices' [patent_app_type] => utility [patent_app_number] => 14/459426 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459426 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459426
Read Methods for Non-Volatile Memory Devices and Related Non-Volatile Memory Devices Aug 13, 2014 Abandoned
Array ( [id] => 10394446 [patent_doc_number] => 20150279453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'MEMORY CIRCUIT HAVING SHARED WORD LINE' [patent_app_type] => utility [patent_app_number] => 14/459094 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459094 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459094
Memory circuit having shared word line Aug 12, 2014 Issued
Array ( [id] => 10925090 [patent_doc_number] => 20140328111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'SIGNAL PROCESSING CIRCUIT AND METHOD FOR DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/332630 [patent_app_country] => US [patent_app_date] => 2014-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 33897 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14332630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/332630
Signal processing circuit and method for driving the same Jul 15, 2014 Issued
Array ( [id] => 10502264 [patent_doc_number] => 09230666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Drain select gate voltage management' [patent_app_type] => utility [patent_app_number] => 14/320068 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320068
Drain select gate voltage management Jun 29, 2014 Issued
Array ( [id] => 10904499 [patent_doc_number] => 20140307512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'TECHNIQUES FOR REDUCING DISTURBANCE IN A SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/313654 [patent_app_country] => US [patent_app_date] => 2014-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14313654 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/313654
Techniques for reducing disturbance in a semiconductor memory device Jun 23, 2014 Issued
Array ( [id] => 9733332 [patent_doc_number] => 20140269042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Self-referenced Magnetic Random Access Memory' [patent_app_type] => utility [patent_app_number] => 14/294239 [patent_app_country] => US [patent_app_date] => 2014-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5535 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14294239 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/294239
Self-referenced magnetic random access memory Jun 2, 2014 Issued
Array ( [id] => 9697977 [patent_doc_number] => 20140247662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'Efficient Smart Verify Method For Programming 3D Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 14/278374 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12151 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14278374 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/278374
Efficient smart verify method for programming 3D non-volatile memory May 14, 2014 Issued
Array ( [id] => 9697974 [patent_doc_number] => 20140247659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/277311 [patent_app_country] => US [patent_app_date] => 2014-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14059 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14277311 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/277311
Reducing weak-erase type read disturb in 3D non-volatile memory May 13, 2014 Issued
Array ( [id] => 9684325 [patent_doc_number] => 20140241088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING COMPLEMENTARY BIT LINE PAIR' [patent_app_type] => utility [patent_app_number] => 14/272575 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7122 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14272575 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/272575
Semiconductor device having complementary bit line pair May 7, 2014 Issued
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