Search

Angelo Trivisonno

Examiner (ID: 14457, Phone: (571)272-5201 , Office: P/1759 )

Most Active Art Unit
1721
Art Unit(s)
1755, 1722, 1759, 1721
Total Applications
851
Issued Applications
395
Pending Applications
109
Abandoned Applications
360

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18464343 [patent_doc_number] => 11688637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Wrap-around contact structures for semiconductor fins [patent_app_type] => utility [patent_app_number] => 17/542191 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 41 [patent_no_of_words] => 16764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542191
Wrap-around contact structures for semiconductor fins Dec 2, 2021 Issued
Array ( [id] => 18433247 [patent_doc_number] => 11678489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Three-dimensional flash memory device including channel structures having enlarged portions [patent_app_type] => utility [patent_app_number] => 17/532271 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 10473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532271
Three-dimensional flash memory device including channel structures having enlarged portions Nov 21, 2021 Issued
Array ( [id] => 18307103 [patent_doc_number] => 20230111003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => FIELD EFFECT TRANSISTORS WITH REDUCED GATE FRINGE AREA AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/529802 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529802
Field effect transistors with reduced gate fringe area and method of making the same Nov 17, 2021 Issued
Array ( [id] => 18464495 [patent_doc_number] => 11688792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Dual self-aligned gate endcap (SAGE) architectures [patent_app_type] => utility [patent_app_number] => 17/526986 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 13917 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526986
Dual self-aligned gate endcap (SAGE) architectures Nov 14, 2021 Issued
Array ( [id] => 19611022 [patent_doc_number] => 12159904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Cell placement optimization [patent_app_type] => utility [patent_app_number] => 17/523033 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523033
Cell placement optimization Nov 9, 2021 Issued
Array ( [id] => 18197642 [patent_doc_number] => 20230051161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => FinFET STANDARD CELL WITH DOUBLE SELF-ALIGNED CONTACTS AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/522781 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522781
FinFET standard cell with double self-aligned contacts and method therefor Nov 8, 2021 Issued
Array ( [id] => 18236057 [patent_doc_number] => 11600624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Semiconductor structure with dielectric fin in memory cell and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/521389 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521389
Semiconductor structure with dielectric fin in memory cell and method for forming the same Nov 7, 2021 Issued
Array ( [id] => 19341502 [patent_doc_number] => 12051699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Semiconductor structure and method for forming same [patent_app_type] => utility [patent_app_number] => 17/520794 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520794
Semiconductor structure and method for forming same Nov 7, 2021 Issued
Array ( [id] => 17431767 [patent_doc_number] => 20220059476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITANCE TO SURFACE MOUNTED DIE [patent_app_type] => utility [patent_app_number] => 17/518504 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518504
Capacitor die embedded in package substrate for providing capacitance to surface mounted die Nov 2, 2021 Issued
Array ( [id] => 18351288 [patent_doc_number] => 20230139399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => STRESSED MATERIAL WITHIN GATE CUT REGION [patent_app_type] => utility [patent_app_number] => 17/516505 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516505
Stressed material within gate cut region Oct 31, 2021 Issued
Array ( [id] => 17402910 [patent_doc_number] => 20220045001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET) AS ANTIFUSE ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/510190 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510190
Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements Oct 24, 2021 Issued
Array ( [id] => 17403102 [patent_doc_number] => 20220045193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK [patent_app_type] => utility [patent_app_number] => 17/506742 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506742 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506742
Nanosheet transistor with asymmetric gate stack Oct 20, 2021 Issued
Array ( [id] => 18319743 [patent_doc_number] => 20230117871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => COMPACT CMOS [patent_app_type] => utility [patent_app_number] => 17/300746 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17300746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/300746
Compact CMOS Oct 17, 2021 Issued
Array ( [id] => 18913108 [patent_doc_number] => 11876096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Field effect transistors with reduced gate fringe area and method of making the same [patent_app_type] => utility [patent_app_number] => 17/496122 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 69 [patent_no_of_words] => 16306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496122
Field effect transistors with reduced gate fringe area and method of making the same Oct 6, 2021 Issued
Array ( [id] => 18308362 [patent_doc_number] => 20230112262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => FIELD EFFECT TRANSISTORS WITH REDUCED GATE FRINGE AREA AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/496099 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496099
Field effect transistors with reduced gate fringe area and method of making the same Oct 6, 2021 Issued
Array ( [id] => 19328828 [patent_doc_number] => 12046517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Self-aligned 3-D epitaxial structures for MOS device fabrication [patent_app_type] => utility [patent_app_number] => 17/495696 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 9007 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495696
Self-aligned 3-D epitaxial structures for MOS device fabrication Oct 5, 2021 Issued
Array ( [id] => 18857594 [patent_doc_number] => 11855191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Vertical FET with contact to gate above active fin [patent_app_type] => utility [patent_app_number] => 17/450121 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450121
Vertical FET with contact to gate above active fin Oct 5, 2021 Issued
Array ( [id] => 19376671 [patent_doc_number] => 12068251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Semiconductor device, layout design method for the same and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/449721 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12037 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449721 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/449721
Semiconductor device, layout design method for the same and method for fabricating the same Sep 30, 2021 Issued
Array ( [id] => 19444489 [patent_doc_number] => 12094778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Fin field-effect transistor device and method of forming [patent_app_type] => utility [patent_app_number] => 17/490922 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/490922
Fin field-effect transistor device and method of forming Sep 29, 2021 Issued
Array ( [id] => 18282707 [patent_doc_number] => 20230098179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => REDUCING BACK POWERING IN I/O CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/489535 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/489535
Reducing back powering in I/O circuits Sep 28, 2021 Issued
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