Search

Anh D. Mai

Examiner (ID: 6717)

Most Active Art Unit
2814
Art Unit(s)
2814, 2889, 2829, 2893
Total Applications
1241
Issued Applications
570
Pending Applications
112
Abandoned Applications
585

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17403114 [patent_doc_number] => 20220045205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => TRENCH GATE POWER SWITCH WITH DOPED REGIONS TO INDUCE BREAKDOWN AT SELECTED AREAS [patent_app_type] => utility [patent_app_number] => 17/388350 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388350
TRENCH GATE POWER SWITCH WITH DOPED REGIONS TO INDUCE BREAKDOWN AT SELECTED AREAS Jul 28, 2021 Pending
Array ( [id] => 17373675 [patent_doc_number] => 20220028727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR DEVICE MANUFACTURING BY THINNING AND DICING [patent_app_type] => utility [patent_app_number] => 17/380250 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380250
SEMICONDUCTOR DEVICE MANUFACTURING BY THINNING AND DICING Jul 19, 2021 Pending
Array ( [id] => 17373674 [patent_doc_number] => 20220028726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => METHOD FOR FORMING A CAPACITIVE ISOLATION TRENCH AND SUBSTRATE COMPRISING SUCH A TRENCH [patent_app_type] => utility [patent_app_number] => 17/376732 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376732
METHOD FOR FORMING A CAPACITIVE ISOLATION TRENCH AND SUBSTRATE COMPRISING SUCH A TRENCH Jul 14, 2021 Abandoned
Array ( [id] => 19428375 [patent_doc_number] => 12087812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Method of manufacturing a semiconductor device utilzing two hard masks and two auxiliary masks to form PN junctions structure [patent_app_type] => utility [patent_app_number] => 17/374046 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 12758 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/374046
Method of manufacturing a semiconductor device utilzing two hard masks and two auxiliary masks to form PN junctions structure Jul 12, 2021 Issued
Array ( [id] => 18113169 [patent_doc_number] => 20230006049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SILICON CARBIDE POWER DEVICE WITH AN ENHANCED JUNCTION FIELD EFFECT TRANSISTOR REGION [patent_app_type] => utility [patent_app_number] => 17/363218 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363218
SILICON CARBIDE POWER DEVICE WITH AN ENHANCED JUNCTION FIELD EFFECT TRANSISTOR REGION Jun 29, 2021 Abandoned
Array ( [id] => 18097736 [patent_doc_number] => 20220416077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => POWER SEMICONDUCTOR DIE WITH IMPROVED THERMAL PERFORMANCE [patent_app_type] => utility [patent_app_number] => 17/357103 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357103
POWER SEMICONDUCTOR DIE WITH IMPROVED THERMAL PERFORMANCE Jun 23, 2021 Pending
Array ( [id] => 18097736 [patent_doc_number] => 20220416077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => POWER SEMICONDUCTOR DIE WITH IMPROVED THERMAL PERFORMANCE [patent_app_type] => utility [patent_app_number] => 17/357103 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357103
POWER SEMICONDUCTOR DIE WITH IMPROVED THERMAL PERFORMANCE Jun 23, 2021 Pending
Array ( [id] => 17145408 [patent_doc_number] => 20210313421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => SIGNAL ISOLATION APPARATUS AND SIGNAL ISOLATION METHOD [patent_app_type] => utility [patent_app_number] => 17/353248 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353248
SIGNAL ISOLATION APPARATUS AND SIGNAL ISOLATION METHOD Jun 20, 2021 Pending
Array ( [id] => 17130663 [patent_doc_number] => 20210305432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/345546 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345546
SEMICONDUCTOR DEVICE Jun 10, 2021 Abandoned
Array ( [id] => 17130362 [patent_doc_number] => 20210305131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/346186 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346186
Semiconductor structure having a silicon active layer formed over a SiGe etch stop layer and an insulating layer with a through silicon via (TSV) passed therethrough Jun 10, 2021 Issued
Array ( [id] => 17295579 [patent_doc_number] => 20210391418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => SUPER JUNCTION POWER DEVICE AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/345472 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345472
SUPER JUNCTION POWER DEVICE AND METHOD OF MAKING THE SAME Jun 10, 2021 Abandoned
Array ( [id] => 17115795 [patent_doc_number] => 20210296392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => Flat Panel Array with the Alignment Marks in Active Area [patent_app_type] => utility [patent_app_number] => 17/339736 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339736
Flat Panel Array with the Alignment Marks in Active Area Jun 3, 2021 Abandoned
Array ( [id] => 17855160 [patent_doc_number] => 20220285203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DOUBLE PATTERNING TECHNIQUES FOR FORMING A DEEP TRENCH ISOLATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/303524 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303524
DOUBLE PATTERNING TECHNIQUES FOR FORMING A DEEP TRENCH ISOLATION STRUCTURE May 31, 2021 Pending
Array ( [id] => 17855160 [patent_doc_number] => 20220285203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DOUBLE PATTERNING TECHNIQUES FOR FORMING A DEEP TRENCH ISOLATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/303524 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303524
DOUBLE PATTERNING TECHNIQUES FOR FORMING A DEEP TRENCH ISOLATION STRUCTURE May 31, 2021 Pending
Array ( [id] => 18595193 [patent_doc_number] => 11744115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Pixel defining layer having column portions in a space between two adjacent columns of subpixel apertures and spacing apart by multiple pairs of adjacent row portions respectively in multiple rows [patent_app_type] => utility [patent_app_number] => 17/322055 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 9435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322055
Pixel defining layer having column portions in a space between two adjacent columns of subpixel apertures and spacing apart by multiple pairs of adjacent row portions respectively in multiple rows May 16, 2021 Issued
Array ( [id] => 17855442 [patent_doc_number] => 20220285485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/317576 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317576
SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME May 10, 2021 Abandoned
Array ( [id] => 17263076 [patent_doc_number] => 20210376061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => POWER MOSFET WITH REDUCED CURRENT LEAKAGE AND METHOD OF FABRICATING THE POWER MOSFET [patent_app_type] => utility [patent_app_number] => 17/236149 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/236149
POWER MOSFET WITH REDUCED CURRENT LEAKAGE AND METHOD OF FABRICATING THE POWER MOSFET Apr 20, 2021 Abandoned
Array ( [id] => 16995672 [patent_doc_number] => 20210234092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => Reduction of Barrier Resistance X Area (RA) Product and Protection of Perpendicular Magnetic Anisotropy (PMA) for Magnetic Device Applications [patent_app_type] => utility [patent_app_number] => 17/230605 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/230605
Method for forming a perpendicular spin torque oscillator (PSTO) including forming a magneto resistive sensor (MR) over a spin torque oscillator (STO) Apr 13, 2021 Issued
Array ( [id] => 16995672 [patent_doc_number] => 20210234092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => Reduction of Barrier Resistance X Area (RA) Product and Protection of Perpendicular Magnetic Anisotropy (PMA) for Magnetic Device Applications [patent_app_type] => utility [patent_app_number] => 17/230605 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/230605
Method for forming a perpendicular spin torque oscillator (PSTO) including forming a magneto resistive sensor (MR) over a spin torque oscillator (STO) Apr 13, 2021 Issued
Array ( [id] => 17901025 [patent_doc_number] => 20220310687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => PIXEL SENSOR INCLUDING A TRANSFER FINFET [patent_app_type] => utility [patent_app_number] => 17/214329 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214329
Method for manufacturing image sensor including forming FinFET transfer gate having a plurality of channel fins above a p-type region Mar 25, 2021 Issued
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