Search

Anh D. Mai

Examiner (ID: 6717)

Most Active Art Unit
2814
Art Unit(s)
2814, 2889, 2829, 2893
Total Applications
1241
Issued Applications
570
Pending Applications
112
Abandoned Applications
585

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17232559 [patent_doc_number] => 20210359116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 17/210492 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210492
SEMICONDUCTOR APPARATUS Mar 22, 2021 Abandoned
Array ( [id] => 17917700 [patent_doc_number] => 20220320096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => CAPACITOR ARRAY STRUCTURE AND PREPARATION METHOD THEREOF AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/310799 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17310799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/310799
CAPACITOR ARRAY STRUCTURE AND PREPARATION METHOD THEREOF AND SEMICONDUCTOR MEMORY DEVICE Mar 14, 2021 Abandoned
Array ( [id] => 16966346 [patent_doc_number] => 20210217845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/198807 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198807
SEMICONDUCTOR DEVICE Mar 10, 2021 Abandoned
Array ( [id] => 16951690 [patent_doc_number] => 20210210382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => METHOD FOR FORMING CONTACT STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/194918 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194918 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194918
METHOD FOR FORMING CONTACT STRUCTURE Mar 7, 2021 Abandoned
Array ( [id] => 18040416 [patent_doc_number] => 20220384633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => Hole Channel Semiconductor Transistor, Manufacturing Method, and Application thereof [patent_app_type] => utility [patent_app_number] => 17/594846 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17594846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/594846
Non-planar two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) including epitaxially growing an n-type buried layer between first channel and second channel and a method of forming the same Mar 2, 2021 Issued
Array ( [id] => 16905079 [patent_doc_number] => 20210183995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/186881 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186881
SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE Feb 25, 2021 Abandoned
Array ( [id] => 17159120 [patent_doc_number] => 20210320171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUPERJUNCTION SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/187022 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187022
SUPERJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUPERJUNCTION SEMICONDUCTOR DEVICE Feb 25, 2021 Abandoned
Array ( [id] => 18857395 [patent_doc_number] => 11854990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Method for forming a semiconductor device having TSV formed through a silicon interposer and a second silicon substrate with cavity covering a second die [patent_app_type] => utility [patent_app_number] => 17/176299 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 3561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/176299
Method for forming a semiconductor device having TSV formed through a silicon interposer and a second silicon substrate with cavity covering a second die Feb 15, 2021 Issued
Array ( [id] => 17486273 [patent_doc_number] => 20220093777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/175233 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175233
SEMICONDUCTOR DEVICE Feb 11, 2021 Abandoned
Array ( [id] => 16995618 [patent_doc_number] => 20210234038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/155782 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155782
SEMICONDUCTOR DEVICE Jan 21, 2021 Abandoned
Array ( [id] => 18158837 [patent_doc_number] => 20230025429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE FOR RADIOFREQUENCY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/757822 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17757822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/757822
METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE FOR RADIOFREQUENCY APPLICATIONS Jan 6, 2021 Pending
Array ( [id] => 16781941 [patent_doc_number] => 20210119020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => BOTTOM SPACER STRUCTURE FOR VERTICAL FIELD EFFECT TRANSISTOR AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/136852 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136852
Vertical transistor having bottom spacers on source/drain regions with different heights along junction region Dec 28, 2020 Issued
Array ( [id] => 17583277 [patent_doc_number] => 20220140132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => PASSIVATION STRUCTURES FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/088686 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088686
PASSIVATION STRUCTURES FOR SEMICONDUCTOR DEVICES Nov 3, 2020 Pending
Array ( [id] => 19739249 [patent_doc_number] => 12216077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => BioFET device having a metal crown structure as a sensing layer disposed on an oxide layer formed under a channel region of a transistor [patent_app_type] => utility [patent_app_number] => 17/087112 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087112 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087112
BioFET device having a metal crown structure as a sensing layer disposed on an oxide layer formed under a channel region of a transistor Nov 1, 2020 Issued
Array ( [id] => 16936805 [patent_doc_number] => 20210202694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/075032 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075032
Semiconductor device comprising a MOSFET having a RESURF region and higher peak impurity concentration diffusion region in the RESURF region Oct 19, 2020 Issued
Array ( [id] => 16602915 [patent_doc_number] => 20210029446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/067696 [patent_app_country] => US [patent_app_date] => 2020-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067696
ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Oct 10, 2020 Pending
Array ( [id] => 17188924 [patent_doc_number] => 20210335809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SEMICONDUCTOR DEVICES HAVING ISOLATION INSULATING LAYERS [patent_app_type] => utility [patent_app_number] => 17/036373 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036373
Semiconductor device having a through electrode penetrating mold layers formed in an extension area Sep 28, 2020 Issued
Array ( [id] => 17448218 [patent_doc_number] => 20220068723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD FOR FORMING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/026319 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026319
METHOD FOR FORMING A SEMICONDUCTOR DEVICE Sep 20, 2020 Abandoned
Array ( [id] => 18137362 [patent_doc_number] => 11563051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Light-emitting diode (LED) light board, spliced led light board and display device having the ends of the first and second signal wires being staggered [patent_app_type] => utility [patent_app_number] => 16/981351 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8282 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16981351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/981351
Light-emitting diode (LED) light board, spliced led light board and display device having the ends of the first and second signal wires being staggered Aug 16, 2020 Issued
Array ( [id] => 16936763 [patent_doc_number] => 20210202652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/991314 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991314 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991314
Display device having a conductive layer of a same material as the pixel electrode covering one side surface of a power supply line formed under a sealing portion between two substrates Aug 11, 2020 Issued
Menu