
Anh K. Phung
Examiner (ID: 5788)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2858, 2818, 2824, 2213 |
| Total Applications | 1586 |
| Issued Applications | 1505 |
| Pending Applications | 37 |
| Abandoned Applications | 44 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5433988
[patent_doc_number] => 20090168574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-02
[patent_title] => 'METHOD OF DRIVING 1-TRANSISTOR TYPE DRAM HAVING AN NMOS OVERLAIN ON TOP OF AN SOI LAYER'
[patent_app_type] => utility
[patent_app_number] => 12/167280
[patent_app_country] => US
[patent_app_date] => 2008-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4506
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20090168574.pdf
[firstpage_image] =>[orig_patent_app_number] => 12167280
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/167280 | Method of driving 1-transistor type DRAM having an NMOS overlain on top of an SOI layer | Jul 2, 2008 | Issued |
Array
(
[id] => 4548615
[patent_doc_number] => 07876606
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-25
[patent_title] => 'Integrated circuit for programming a memory cell'
[patent_app_type] => utility
[patent_app_number] => 12/166755
[patent_app_country] => US
[patent_app_date] => 2008-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4276
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/876/07876606.pdf
[firstpage_image] =>[orig_patent_app_number] => 12166755
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/166755 | Integrated circuit for programming a memory cell | Jul 1, 2008 | Issued |
Array
(
[id] => 7970029
[patent_doc_number] => 07940589
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Bit line sense amplifier of semiconductor memory device and control method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/166525
[patent_app_country] => US
[patent_app_date] => 2008-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5251
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/940/07940589.pdf
[firstpage_image] =>[orig_patent_app_number] => 12166525
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/166525 | Bit line sense amplifier of semiconductor memory device and control method thereof | Jul 1, 2008 | Issued |
Array
(
[id] => 7022
[patent_doc_number] => 07813189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-12
[patent_title] => 'Array data input latch and data clocking scheme'
[patent_app_type] => utility
[patent_app_number] => 12/166421
[patent_app_country] => US
[patent_app_date] => 2008-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2803
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/813/07813189.pdf
[firstpage_image] =>[orig_patent_app_number] => 12166421
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/166421 | Array data input latch and data clocking scheme | Jul 1, 2008 | Issued |
Array
(
[id] => 5433972
[patent_doc_number] => 20090168558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-02
[patent_title] => '1-TRANSISTOR TYPE DRAM DRIVING METHOD WITH AN IMPROVED WRITE OPERATION MARGIN'
[patent_app_type] => utility
[patent_app_number] => 12/166753
[patent_app_country] => US
[patent_app_date] => 2008-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 4726
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20090168558.pdf
[firstpage_image] =>[orig_patent_app_number] => 12166753
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/166753 | 1-transistor type DRAM driving method with an improved write operation margin | Jul 1, 2008 | Issued |
Array
(
[id] => 5408701
[patent_doc_number] => 20090122599
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-14
[patent_title] => 'WRITING SYSTEM AND METHOD FOR PHASE CHANGE MOMORY'
[patent_app_type] => utility
[patent_app_number] => 12/165761
[patent_app_country] => US
[patent_app_date] => 2008-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3396
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20090122599.pdf
[firstpage_image] =>[orig_patent_app_number] => 12165761
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/165761 | Writing system and method for phase change memory | Jun 30, 2008 | Issued |
Array
(
[id] => 4577249
[patent_doc_number] => 07848155
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-07
[patent_title] => 'Non-volatile memory system including spare array and method of erasing a block in the same'
[patent_app_type] => utility
[patent_app_number] => 12/165861
[patent_app_country] => US
[patent_app_date] => 2008-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4701
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/848/07848155.pdf
[firstpage_image] =>[orig_patent_app_number] => 12165861
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/165861 | Non-volatile memory system including spare array and method of erasing a block in the same | Jun 30, 2008 | Issued |
Array
(
[id] => 5295164
[patent_doc_number] => 20090010090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-08
[patent_title] => 'BUCKET BRIGADE ADDRESS DECODING ARCHITECTURE FOR CLASSICAL AND QUANTUM RANDOM ACCESS MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 12/166307
[patent_app_country] => US
[patent_app_date] => 2008-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5559
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20090010090.pdf
[firstpage_image] =>[orig_patent_app_number] => 12166307
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/166307 | Bucket brigade address decoding architecture for classical and quantum random access memories | Jun 30, 2008 | Issued |
Array
(
[id] => 154421
[patent_doc_number] => 07679949
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-03-16
[patent_title] => 'Column select multiplexer circuit for a domino random access memory array'
[patent_app_type] => utility
[patent_app_number] => 12/165432
[patent_app_country] => US
[patent_app_date] => 2008-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 4
[patent_no_of_words] => 3771
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/679/07679949.pdf
[firstpage_image] =>[orig_patent_app_number] => 12165432
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/165432 | Column select multiplexer circuit for a domino random access memory array | Jun 29, 2008 | Issued |
Array
(
[id] => 26180
[patent_doc_number] => 07796443
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-14
[patent_title] => 'Method of erasing a flash EEPROM memory'
[patent_app_type] => utility
[patent_app_number] => 12/137937
[patent_app_country] => US
[patent_app_date] => 2008-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4580
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/796/07796443.pdf
[firstpage_image] =>[orig_patent_app_number] => 12137937
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/137937 | Method of erasing a flash EEPROM memory | Jun 11, 2008 | Issued |
Array
(
[id] => 26195
[patent_doc_number] => 07796452
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-14
[patent_title] => 'Semiconductor memory device maintaining word line driving voltage'
[patent_app_type] => utility
[patent_app_number] => 12/137663
[patent_app_country] => US
[patent_app_date] => 2008-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2355
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/796/07796452.pdf
[firstpage_image] =>[orig_patent_app_number] => 12137663
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/137663 | Semiconductor memory device maintaining word line driving voltage | Jun 11, 2008 | Issued |
Array
(
[id] => 5308853
[patent_doc_number] => 20090016134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-15
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/137065
[patent_app_country] => US
[patent_app_date] => 2008-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9151
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0016/20090016134.pdf
[firstpage_image] =>[orig_patent_app_number] => 12137065
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/137065 | Semiconductor memory device | Jun 10, 2008 | Issued |
Array
(
[id] => 5421155
[patent_doc_number] => 20090147610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-11
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/137069
[patent_app_country] => US
[patent_app_date] => 2008-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9993
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0147/20090147610.pdf
[firstpage_image] =>[orig_patent_app_number] => 12137069
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/137069 | Semiconductor device | Jun 10, 2008 | Issued |
Array
(
[id] => 35026
[patent_doc_number] => 07791957
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'Semiconductor integrated circuit and method of allocating codes'
[patent_app_type] => utility
[patent_app_number] => 12/136453
[patent_app_country] => US
[patent_app_date] => 2008-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 31
[patent_no_of_words] => 12188
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/791/07791957.pdf
[firstpage_image] =>[orig_patent_app_number] => 12136453
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/136453 | Semiconductor integrated circuit and method of allocating codes | Jun 9, 2008 | Issued |
Array
(
[id] => 55614
[patent_doc_number] => 07773448
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-10
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/136487
[patent_app_country] => US
[patent_app_date] => 2008-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4417
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/773/07773448.pdf
[firstpage_image] =>[orig_patent_app_number] => 12136487
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/136487 | Semiconductor memory device | Jun 9, 2008 | Issued |
Array
(
[id] => 7589497
[patent_doc_number] => 07663910
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-16
[patent_title] => 'Phase change memory device'
[patent_app_type] => utility
[patent_app_number] => 12/135241
[patent_app_country] => US
[patent_app_date] => 2008-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 8993
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/663/07663910.pdf
[firstpage_image] =>[orig_patent_app_number] => 12135241
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/135241 | Phase change memory device | Jun 8, 2008 | Issued |
Array
(
[id] => 24654
[patent_doc_number] => 07800955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Programming method of a non-volatile memory device'
[patent_app_type] => utility
[patent_app_number] => 12/134943
[patent_app_country] => US
[patent_app_date] => 2008-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6423
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/800/07800955.pdf
[firstpage_image] =>[orig_patent_app_number] => 12134943
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/134943 | Programming method of a non-volatile memory device | Jun 5, 2008 | Issued |
Array
(
[id] => 4717273
[patent_doc_number] => 20080239795
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'NONVOLATILE MEMORY DEVICE WITH WRITE ERROR SUPPRESSED IN READING DATA'
[patent_app_type] => utility
[patent_app_number] => 12/133519
[patent_app_country] => US
[patent_app_date] => 2008-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 13510
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20080239795.pdf
[firstpage_image] =>[orig_patent_app_number] => 12133519
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/133519 | NONVOLATILE MEMORY DEVICE WITH WRITE ERROR SUPPRESSED IN READING DATA | Jun 4, 2008 | Abandoned |
Array
(
[id] => 4948183
[patent_doc_number] => 20080304309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-11
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/132713
[patent_app_country] => US
[patent_app_date] => 2008-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6625
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0304/20080304309.pdf
[firstpage_image] =>[orig_patent_app_number] => 12132713
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/132713 | Semiconductor memory device | Jun 3, 2008 | Issued |
Array
(
[id] => 192033
[patent_doc_number] => 07643352
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'Method for erasing flash memory'
[patent_app_type] => utility
[patent_app_number] => 12/132153
[patent_app_country] => US
[patent_app_date] => 2008-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1405
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/643/07643352.pdf
[firstpage_image] =>[orig_patent_app_number] => 12132153
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/132153 | Method for erasing flash memory | Jun 2, 2008 | Issued |