Anil N. Kumar

Array ( [id] => 4374605 [patent_doc_number] => 06219629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Apparatus for combined simulation of electromagnetic wave analysis and circuit analysis, and computer-readable medium containing simulation program therefor' [patent_app_type] => 1 [patent_app_number] => 9/076069 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6390 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219629.pdf [firstpage_image] =>[orig_patent_app_number] => 076069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4144919 [patent_doc_number] => 06102959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Verification tool computation reduction' [patent_app_type] => 1 [patent_app_number] => 9/067437 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4682 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/102/06102959.pdf [firstpage_image] =>[orig_patent_app_number] => 067437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3966498 [patent_doc_number] => 05999725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method and apparatus tracing any node of an emulation' [patent_app_type] => 1 [patent_app_number] => 9/062240 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4085 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999725.pdf [firstpage_image] =>[orig_patent_app_number] => 062240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108017 [patent_doc_number] => 06134511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method and apparatus for improving building energy simulations' [patent_app_type] => 1 [patent_app_number] => 9/060734 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14331 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134511.pdf [firstpage_image] =>[orig_patent_app_number] => 060734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4191024 [patent_doc_number] => 06141631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Pulse rejection circuit model program and technique in VHDL' [patent_app_type] => 1 [patent_app_number] => 9/047877 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4894 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141631.pdf [firstpage_image] =>[orig_patent_app_number] => 047877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4158534 [patent_doc_number] => 06031986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Thin-film passive circuit simulation on basis of reduced equivalent circuits' [patent_app_type] => 1 [patent_app_number] => 9/047153 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6776 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031986.pdf [firstpage_image] =>[orig_patent_app_number] => 047153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4086511 [patent_doc_number] => 06096085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Computer-readable software and computer-implemented method for performing an integrated sonar simulation' [patent_app_type] => 1 [patent_app_number] => 9/049660 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 13169 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096085.pdf [firstpage_image] =>[orig_patent_app_number] => 049660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423849 [patent_doc_number] => 06230117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'System for automated interface generation for computer programs operating in different environments' [patent_app_type] => 1 [patent_app_number] => 9/046366 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3965 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230117.pdf [firstpage_image] =>[orig_patent_app_number] => 046366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4249219 [patent_doc_number] => 06075937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation' [patent_app_type] => 1 [patent_app_number] => 9/040671 [patent_app_country] => US [patent_app_date] => 1998-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 14585 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075937.pdf [firstpage_image] =>[orig_patent_app_number] => 040671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4226311 [patent_doc_number] => 06074426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method for automatically generating behavioral environment for model checking' [patent_app_type] => 1 [patent_app_number] => 9/042373 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3196 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074426.pdf [firstpage_image] =>[orig_patent_app_number] => 042373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4195219 [patent_doc_number] => 06038391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method and apparatus for evaluating performance of multi-processing system and memory medium storing program for the same' [patent_app_type] => 1 [patent_app_number] => 9/037850 [patent_app_country] => US [patent_app_date] => 1998-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5957 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038391.pdf [firstpage_image] =>[orig_patent_app_number] => 037850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4379389 [patent_doc_number] => 06256595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Apparatus and method for manually selecting, displaying, and repositioning dimensions of a part model' [patent_app_type] => 1 [patent_app_number] => 9/034356 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 14217 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256595.pdf [firstpage_image] =>[orig_patent_app_number] => 034356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4144944 [patent_doc_number] => 06102960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Automatic behavioral model generation through physical component characterization and measurement' [patent_app_type] => 1 [patent_app_number] => 9/027950 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7118 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/102/06102960.pdf [firstpage_image] =>[orig_patent_app_number] => 027950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4099863 [patent_doc_number] => 06026221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Prototyping multichip module' [patent_app_type] => 1 [patent_app_number] => 9/025671 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2553 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026221.pdf [firstpage_image] =>[orig_patent_app_number] => 025671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4052768 [patent_doc_number] => 05995744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Network configuration of programmable circuits' [patent_app_type] => 1 [patent_app_number] => 9/023334 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4921 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995744.pdf [firstpage_image] =>[orig_patent_app_number] => 023334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1517592 [patent_doc_number] => 06421251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Array board interconnect system and method' [patent_app_type] => B1 [patent_app_number] => 09/019383 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 76 [patent_no_of_words] => 69629 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421251.pdf [firstpage_image] =>[orig_patent_app_number] => 09019383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4100001 [patent_doc_number] => 06026230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Memory simulation system and method' [patent_app_type] => 1 [patent_app_number] => 9/019328 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 76 [patent_no_of_words] => 70170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026230.pdf [firstpage_image] =>[orig_patent_app_number] => 019328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108080 [patent_doc_number] => 06134515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Controlling a first type telecommunications switch upon translating instructions for a second type telecommunications switch' [patent_app_type] => 1 [patent_app_number] => 9/016355 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10589 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134515.pdf [firstpage_image] =>[orig_patent_app_number] => 016355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4144397 [patent_doc_number] => 06106566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Upgradable electronic module and system using same' [patent_app_type] => 1 [patent_app_number] => 9/015855 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2103 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/106/06106566.pdf [firstpage_image] =>[orig_patent_app_number] => 015855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131306 [patent_doc_number] => 06059836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Logic circuit emulator' [patent_app_type] => 1 [patent_app_number] => 9/014359 [patent_app_country] => US [patent_app_date] => 1998-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3726 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/059/06059836.pdf [firstpage_image] =>[orig_patent_app_number] => 014359 [rel_patent_id] =>[rel_patent_doc_number] =>)