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Anjeanette Roberts

Examiner (ID: 9441)

Most Active Art Unit
1633
Art Unit(s)
1633
Total Applications
28
Issued Applications
18
Pending Applications
0
Abandoned Applications
10

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16425298 [patent_doc_number] => 20200350496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => METHODS FOR FORMING NARROW VERTICAL PILLARS AND INTEGRATED CIRCUIT DEVICES HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 16/934844 [patent_app_country] => US [patent_app_date] => 2020-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/934844
Methods for forming narrow vertical pillars and integrated circuit devices having the same Jul 20, 2020 Issued
Array ( [id] => 16402508 [patent_doc_number] => 20200343366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => FIN CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 16/925573 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925573
Fin cut and fin trim isolation for advanced integrated circuit structure fabrication Jul 9, 2020 Issued
Array ( [id] => 16410055 [patent_doc_number] => 10818619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-27 [patent_title] => Chip packages and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/919447 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2868 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/919447
Chip packages and methods for forming the same Jul 1, 2020 Issued
Array ( [id] => 16410055 [patent_doc_number] => 10818619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-27 [patent_title] => Chip packages and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/919447 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2868 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/919447
Chip packages and methods for forming the same Jul 1, 2020 Issued
Array ( [id] => 16410055 [patent_doc_number] => 10818619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-27 [patent_title] => Chip packages and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/919447 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2868 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/919447
Chip packages and methods for forming the same Jul 1, 2020 Issued
Array ( [id] => 16410055 [patent_doc_number] => 10818619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-27 [patent_title] => Chip packages and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/919447 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2868 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/919447
Chip packages and methods for forming the same Jul 1, 2020 Issued
Array ( [id] => 16394751 [patent_doc_number] => 20200335692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/916227 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916227 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916227
Semiconductor devices Jun 29, 2020 Issued
Array ( [id] => 17758300 [patent_doc_number] => 11398599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Methods for forming memory devices, and associated devices and systems [patent_app_type] => utility [patent_app_number] => 16/914887 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4102 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914887 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914887
Methods for forming memory devices, and associated devices and systems Jun 28, 2020 Issued
Array ( [id] => 16379538 [patent_doc_number] => 20200328381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => MANUFACTURING METHOD OF THE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/911481 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911481
Manufacturing method of the display device Jun 24, 2020 Issued
Array ( [id] => 16495798 [patent_doc_number] => 10861850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Fin end plug structures for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 16/906680 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 225 [patent_no_of_words] => 73452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906680
Fin end plug structures for advanced integrated circuit structure fabrication Jun 18, 2020 Issued
Array ( [id] => 16528770 [patent_doc_number] => 20200402851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => Roughening of a Metallization Layer on a Semiconductor Wafer [patent_app_type] => utility [patent_app_number] => 16/906586 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906586 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906586
Roughening of a metallization layer on a semiconductor wafer Jun 18, 2020 Issued
Array ( [id] => 16774143 [patent_doc_number] => 10985267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication [patent_app_type] => utility [patent_app_number] => 16/906427 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 121 [patent_figures_cnt] => 224 [patent_no_of_words] => 73647 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906427 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906427
Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication Jun 18, 2020 Issued
Array ( [id] => 17381173 [patent_doc_number] => 11239206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Dual sided fan-out package having low warpage across all temperatures [patent_app_type] => utility [patent_app_number] => 16/905435 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 7423 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905435 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905435
Dual sided fan-out package having low warpage across all temperatures Jun 17, 2020 Issued
Array ( [id] => 17295513 [patent_doc_number] => 20210391352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Integrated Assemblies and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 16/902897 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902897
Integrated assemblies and methods of forming integrated assemblies Jun 15, 2020 Issued
Array ( [id] => 16348229 [patent_doc_number] => 20200312880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => Methods Used In Forming An Array Of Elevationally-Extending Transistors [patent_app_type] => utility [patent_app_number] => 16/903201 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903201
Methods used in forming an array of elevationally-extending transistors Jun 15, 2020 Issued
Array ( [id] => 16348226 [patent_doc_number] => 20200312877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/901171 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/901171
Semiconductor memory device and method of manufacturing the same Jun 14, 2020 Issued
Array ( [id] => 17668302 [patent_doc_number] => 11362006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/889160 [patent_app_country] => US [patent_app_date] => 2020-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/889160
Semiconductor device and method of manufacture May 31, 2020 Issued
Array ( [id] => 16752656 [patent_doc_number] => 20210104668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => ELECTRONIC DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/883770 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883770 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/883770
Electronic device and operating method of electronic device May 25, 2020 Issued
Array ( [id] => 16301050 [patent_doc_number] => 20200286773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => CYCLIC FLOWABLE DEPOSITION AND HIGH-DENSITY PLASMA TREATMENT PROCESSES FOR HIGH QUALITY GAP FILL SOLUTIONS [patent_app_type] => utility [patent_app_number] => 16/882989 [patent_app_country] => US [patent_app_date] => 2020-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882989 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882989
Cyclic flowable deposition and high-density plasma treatment processes for high quality gap fill solutions May 25, 2020 Issued
Array ( [id] => 16286208 [patent_doc_number] => 20200279810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => 3D NAND WORD LINE CONNECTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/879541 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879541 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/879541
3D NAND word line connection structure May 19, 2020 Issued
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