Search

Ankush K. Singal

Examiner (ID: 8743, Phone: (571)270-1204 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2823
Total Applications
907
Issued Applications
775
Pending Applications
4
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11694353 [patent_doc_number] => 20170170069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/131704 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131704 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/131704
Method for manufacturing semiconductor device Apr 17, 2016 Issued
Array ( [id] => 11036201 [patent_doc_number] => 20160233157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'SLOT DESIGNS IN WIDE METAL LINES' [patent_app_type] => utility [patent_app_number] => 15/132199 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132199 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132199
SLOT DESIGNS IN WIDE METAL LINES Apr 17, 2016 Abandoned
Array ( [id] => 12047247 [patent_doc_number] => 09824857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Method for implantation of semiconductor wafers having high bulk resistivity' [patent_app_type] => utility [patent_app_number] => 15/131520 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131520 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/131520
Method for implantation of semiconductor wafers having high bulk resistivity Apr 17, 2016 Issued
Array ( [id] => 11110881 [patent_doc_number] => 20160307851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'METHOD OF DIVIDING WAFER' [patent_app_type] => utility [patent_app_number] => 15/131887 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4595 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131887 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/131887
METHOD OF DIVIDING WAFER Apr 17, 2016 Abandoned
Array ( [id] => 11997387 [patent_doc_number] => 20170301542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'COMBINED ANNEAL AND SELECTIVE DEPOSITION PROCESS' [patent_app_type] => utility [patent_app_number] => 15/132091 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2915 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132091
Combined anneal and selective deposition process Apr 17, 2016 Issued
Array ( [id] => 11489385 [patent_doc_number] => 09595458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Plasma processing apparatus and method, and method of manufacturing electronic device' [patent_app_type] => utility [patent_app_number] => 15/131816 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 7621 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131816 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/131816
Plasma processing apparatus and method, and method of manufacturing electronic device Apr 17, 2016 Issued
Array ( [id] => 11585794 [patent_doc_number] => 09640445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-02 [patent_title] => 'Methods of fabricating switched-capacitor DC-to-DC converters' [patent_app_type] => utility [patent_app_number] => 15/130806 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6214 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130806 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/130806
Methods of fabricating switched-capacitor DC-to-DC converters Apr 14, 2016 Issued
Array ( [id] => 13893345 [patent_doc_number] => 10199225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Substrate processing apparatus [patent_app_type] => utility [patent_app_number] => 15/566695 [patent_app_country] => US [patent_app_date] => 2016-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8956 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15566695 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/566695
Substrate processing apparatus Apr 11, 2016 Issued
Array ( [id] => 11000238 [patent_doc_number] => 20160197185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL' [patent_app_type] => utility [patent_app_number] => 15/069726 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15069726 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/069726
Method for fabricating transistor with thinned channel Mar 13, 2016 Issued
Array ( [id] => 11551780 [patent_doc_number] => 09620641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'FinFET with epitaxial source and drain regions and dielectric isolated channel region' [patent_app_type] => utility [patent_app_number] => 15/049796 [patent_app_country] => US [patent_app_date] => 2016-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 9916 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049796 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/049796
FinFET with epitaxial source and drain regions and dielectric isolated channel region Feb 21, 2016 Issued
Array ( [id] => 11466917 [patent_doc_number] => 09583558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'High breakdown voltage microelectronic device isolation structure with improved reliability' [patent_app_type] => utility [patent_app_number] => 15/045421 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 7650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045421 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045421
High breakdown voltage microelectronic device isolation structure with improved reliability Feb 16, 2016 Issued
Array ( [id] => 10817622 [patent_doc_number] => 20160163785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'High Breakdown Voltage Microelectronic Device Isolation Structure with Improved Reliability' [patent_app_type] => utility [patent_app_number] => 15/045449 [patent_app_country] => US [patent_app_date] => 2016-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 7651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045449
High breakdown voltage microelectronic device isolation structure with improved reliability Feb 16, 2016 Issued
Array ( [id] => 10806309 [patent_doc_number] => 20160152467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'MEMS CAPPING METHOD' [patent_app_type] => utility [patent_app_number] => 15/018740 [patent_app_country] => US [patent_app_date] => 2016-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4332 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018740 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/018740
MEMS capping method Feb 7, 2016 Issued
Array ( [id] => 11432224 [patent_doc_number] => 09570551 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Replacement III-V or germanium nanowires by unilateral confined epitaxial growth' [patent_app_type] => utility [patent_app_number] => 15/016875 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 9243 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016875 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016875
Replacement III-V or germanium nanowires by unilateral confined epitaxial growth Feb 4, 2016 Issued
Array ( [id] => 11645208 [patent_doc_number] => 09666600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Direct bandgap substrates and methods of making and using' [patent_app_type] => utility [patent_app_number] => 15/009284 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 9341 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009284 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/009284
Direct bandgap substrates and methods of making and using Jan 27, 2016 Issued
Array ( [id] => 10795204 [patent_doc_number] => 20160141361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN' [patent_app_type] => utility [patent_app_number] => 15/004005 [patent_app_country] => US [patent_app_date] => 2016-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15004005 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/004005
Nanowire MOSFET with support structures for source and drain Jan 21, 2016 Issued
Array ( [id] => 10802766 [patent_doc_number] => 20160148923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 15/001767 [patent_app_country] => US [patent_app_date] => 2016-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12415 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15001767 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/001767
Semiconductor device and manufacturing method of the same Jan 19, 2016 Issued
Array ( [id] => 11681555 [patent_doc_number] => 09680090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Plasma etching method' [patent_app_type] => utility [patent_app_number] => 14/995897 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5715 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995897 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995897
Plasma etching method Jan 13, 2016 Issued
Array ( [id] => 11681555 [patent_doc_number] => 09680090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Plasma etching method' [patent_app_type] => utility [patent_app_number] => 14/995897 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5715 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995897 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995897
Plasma etching method Jan 13, 2016 Issued
Array ( [id] => 10984210 [patent_doc_number] => 20160181155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHOD FOR MAKING AN INTEGRATED CIRCUIT IN THREE DIMENSIONS' [patent_app_type] => utility [patent_app_number] => 14/976958 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6641 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976958 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/976958
METHOD FOR MAKING AN INTEGRATED CIRCUIT IN THREE DIMENSIONS Dec 20, 2015 Abandoned
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