Search

Anna L. Verderame

Examiner (ID: 19741)

Most Active Art Unit
1795
Art Unit(s)
1722, 1756, 1795
Total Applications
250
Issued Applications
70
Pending Applications
1
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15598107 [patent_doc_number] => 20200075588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => Methods of Manufacturing Transistor Gate Structures by Local Thinning of Dummy Gate Stacks Using an Etch Barrier [patent_app_type] => utility [patent_app_number] => 16/675856 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16675856 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/675856
FinFETs with locally thinned gate structures and having different distances therebetween Nov 5, 2019 Issued
Array ( [id] => 16803366 [patent_doc_number] => 10998321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => Semiconductor device having a stacked nanowire structure disposed over a buried word line and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/665451 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16665451 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/665451
Semiconductor device having a stacked nanowire structure disposed over a buried word line and method of manufacturing the same Oct 27, 2019 Issued
Array ( [id] => 16796190 [patent_doc_number] => 20210126007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING STACKED DATA LINES [patent_app_type] => utility [patent_app_number] => 16/664280 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664280 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664280
Semiconductor device having a stack of data lines with conductive structures on both sides thereof Oct 24, 2019 Issued
Array ( [id] => 17493636 [patent_doc_number] => 11282954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => LDMOS device with integrated P-N junction diodes [patent_app_type] => utility [patent_app_number] => 16/664121 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4220 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664121 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664121
LDMOS device with integrated P-N junction diodes Oct 24, 2019 Issued
Array ( [id] => 17048020 [patent_doc_number] => 11101210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Methods for manufacturing a memory array having strings of memory cells comprising forming bridge material between memory blocks [patent_app_type] => utility [patent_app_number] => 16/664618 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 40 [patent_no_of_words] => 6971 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664618
Methods for manufacturing a memory array having strings of memory cells comprising forming bridge material between memory blocks Oct 24, 2019 Issued
Array ( [id] => 15943189 [patent_doc_number] => 20200163228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => PRINTED CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 16/664113 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664113 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664113
PRINTED CIRCUIT BOARD Oct 24, 2019 Abandoned
Array ( [id] => 16796177 [patent_doc_number] => 20210125994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => Methods for Forming Dynamic Random-Access Devices by Implanting a Drain through a Spacer Opening at the Bottom of Angled Structures [patent_app_type] => utility [patent_app_number] => 16/664107 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16664107 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/664107
Methods for forming dynamic random-access devices by implanting a drain through a spacer opening at the bottom of angled structures Oct 24, 2019 Issued
Array ( [id] => 15906681 [patent_doc_number] => 20200152861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/663800 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663800
Semiconductor device having a vertical hall element with a buried layer Oct 24, 2019 Issued
Array ( [id] => 17239611 [patent_doc_number] => 11183503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Memory cell having top and bottom electrodes defining recesses [patent_app_type] => utility [patent_app_number] => 16/663952 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 8479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663952
Memory cell having top and bottom electrodes defining recesses Oct 24, 2019 Issued
Array ( [id] => 16796102 [patent_doc_number] => 20210125919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells [patent_app_type] => utility [patent_app_number] => 16/663683 [patent_app_country] => US [patent_app_date] => 2019-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663683 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663683
Methods used in forming a memory array comprising strings of memory cells Oct 24, 2019 Issued
Array ( [id] => 16218678 [patent_doc_number] => 10734501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Metal gate structure having gate metal layer with a top portion width smaller than a bottom portion width to reduce transistor gate resistance [patent_app_type] => utility [patent_app_number] => 16/661320 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4822 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661320
Metal gate structure having gate metal layer with a top portion width smaller than a bottom portion width to reduce transistor gate resistance Oct 22, 2019 Issued
Array ( [id] => 15503791 [patent_doc_number] => 20200052084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/655079 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655079
Semiconductor device with gate-all-around (GAA) FETs having inner insulating spacers Oct 15, 2019 Issued
Array ( [id] => 16707709 [patent_doc_number] => 10957653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Methods for manufacturing semiconductor arrangements using photoresist masks [patent_app_type] => utility [patent_app_number] => 16/599366 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599366
Methods for manufacturing semiconductor arrangements using photoresist masks Oct 10, 2019 Issued
Array ( [id] => 18396851 [patent_doc_number] => 20230165072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/964169 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16964169 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/964169
Display panel having a light shielding layer with an imaging pinhole at select minimum distances from color sub-pixels, a manufacturing method thereof, and display device Sep 26, 2019 Issued
Array ( [id] => 18578984 [patent_doc_number] => 11735524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Electrical device having conductive lines with air gaps therebetween and interconnects without exclusion zones [patent_app_type] => utility [patent_app_number] => 16/576201 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8065 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576201
Electrical device having conductive lines with air gaps therebetween and interconnects without exclusion zones Sep 18, 2019 Issued
Array ( [id] => 15718111 [patent_doc_number] => 20200105823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => Imaging Device having a Diffusion Region Electrically Connected to a Photoelectric Converter and Overlapping a Region Penetrating another Region of Opposite Conductivity [patent_app_type] => utility [patent_app_number] => 16/566873 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566873 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566873
Imaging device having a diffusion region electrically connected to a photoelectric converter and overlapping a region penetrating another region of opposite conductivity Sep 10, 2019 Issued
Array ( [id] => 15045845 [patent_doc_number] => 20190333927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/508577 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/508577
Semiconductor memory device having an array chip bonded to a circuit chip by a bonding metal Jul 10, 2019 Issued
Array ( [id] => 16609471 [patent_doc_number] => 10910487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Power semiconductor device having trench electrodes biased at three different electrical potentials, and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/456191 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456191 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/456191
Power semiconductor device having trench electrodes biased at three different electrical potentials, and method of manufacturing the same Jun 27, 2019 Issued
Array ( [id] => 14999953 [patent_doc_number] => 20190318934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => SEMICONDUCTOR WAFER AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/453595 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453595 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453595
Electronic device with a gate insulating film and a cap layer of silicon nitride having crystallinity Jun 25, 2019 Issued
Array ( [id] => 14938805 [patent_doc_number] => 20190305041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => DENSITY-CONTROLLABLE DUMMY FILL STRATEGY FOR NEAR-MRAM PERIPHERY AND FAR-OUTSIDE-MRAM LOGIC REGIONS FOR EMBEDDED MRAM TECHNOLOGY AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 16/443255 [patent_app_country] => US [patent_app_date] => 2019-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443255 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/443255
Memory device with density-controllable dummy fill strategy for near-MRAM periphery and far-outside-MRAM logic regions for embedded MRAM technology Jun 16, 2019 Issued
Menu