Search

Anna L. Verderame

Examiner (ID: 19741)

Most Active Art Unit
1795
Art Unit(s)
1722, 1756, 1795
Total Applications
250
Issued Applications
70
Pending Applications
1
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12876526 [patent_doc_number] => 20180184017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => PHOTOELECTRIC CONVERSION DEVICE AND IMAGING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/845995 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845995 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845995
Photoelectric conversion device with a voltage control unit connected to a reset transistor and a capacitive element, and associated imaging system Dec 17, 2017 Issued
Array ( [id] => 16746462 [patent_doc_number] => 10971463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Interconnection structure including a metal post encapsulated by a joint material having concave outer surface [patent_app_type] => utility [patent_app_number] => 15/797623 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797623 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797623
Interconnection structure including a metal post encapsulated by a joint material having concave outer surface Oct 29, 2017 Issued
Array ( [id] => 12181685 [patent_doc_number] => 20180040621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'Structure and Method for MOSFET Device' [patent_app_type] => utility [patent_app_number] => 15/784335 [patent_app_country] => US [patent_app_date] => 2017-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/784335
Methods for manufacturing a fin-based semiconductor device including a metal gate diffusion break structure with a conformal dielectric layer Oct 15, 2017 Issued
Array ( [id] => 12778960 [patent_doc_number] => 20180151488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/716261 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716261
Method of manufacturing an interconnect structure by forming metal layers in mask openings Sep 25, 2017 Issued
Array ( [id] => 13528277 [patent_doc_number] => 20180315681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => INTEGRATED CIRCUIT DIRECT COOLING SYSTEMS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 15/714539 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714539 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714539
Semiconductor package having junction cooling pipes embedded in substrates Sep 24, 2017 Issued
Array ( [id] => 12263748 [patent_doc_number] => 20180082944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/704669 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10960 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704669 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704669
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD Sep 13, 2017 Abandoned
Array ( [id] => 14051031 [patent_doc_number] => 20190081623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => HIGH CURRENT LATERAL GaN TRANSISTORS WITH SCALABLE TOPOLOGY AND GATE DRIVE PHASE EQUALIZATION [patent_app_type] => utility [patent_app_number] => 15/704458 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704458 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704458
High current lateral GaN transistors with scalable topology and gate drive phase equalization Sep 13, 2017 Issued
Array ( [id] => 13452407 [patent_doc_number] => 20180277746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => MAGNETIC MEMORY [patent_app_type] => utility [patent_app_number] => 15/704867 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704867 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704867
Spin orbit torque (SOT) MRAM having a source line connected to a spin orbit conductive layer and arranged above a magnetoresistive element Sep 13, 2017 Issued
Array ( [id] => 14049705 [patent_doc_number] => 20190080960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => Interconnection Structure and Manufacturing Method Thereof [patent_app_type] => utility [patent_app_number] => 15/704202 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704202 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704202
Interconnection structure having top and bottom vias with a barrier layer therebetween and a dielectric spacer at the bottom via Sep 13, 2017 Issued
Array ( [id] => 12243446 [patent_doc_number] => 20180076309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'POWER SEMICONDUCTOR DEVICE WITH DV/DT CONTROLLABILITY' [patent_app_type] => utility [patent_app_number] => 15/704269 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704269 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704269
Power semiconductor device with dV/dt controllability through select trench electrode biasing, and method of manufacturing the same Sep 13, 2017 Issued
Array ( [id] => 14036217 [patent_doc_number] => 10229864 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-12 [patent_title] => Cryogenic integrated circuit having a heat sink coupled to separate ground planes through differently sized thermal vias [patent_app_type] => utility [patent_app_number] => 15/704919 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3339 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704919 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704919
Cryogenic integrated circuit having a heat sink coupled to separate ground planes through differently sized thermal vias Sep 13, 2017 Issued
Array ( [id] => 12896572 [patent_doc_number] => 20180190699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 15/704690 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704690 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704690
Image sensor having a photoelectric conversion layer coupled to a storage node through a pinning layer with P-type impurities Sep 13, 2017 Issued
Array ( [id] => 14268151 [patent_doc_number] => 10283648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => PN junction-based electrical fuse using reverse-bias breakdown to induce an open conduction state [patent_app_type] => utility [patent_app_number] => 15/704617 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4812 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704617 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704617
PN junction-based electrical fuse using reverse-bias breakdown to induce an open conduction state Sep 13, 2017 Issued
Array ( [id] => 13862305 [patent_doc_number] => 10192878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Three-dimensional memory device with self-aligned multi-level drain select gate electrodes [patent_app_type] => utility [patent_app_number] => 15/704286 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 41 [patent_no_of_words] => 16733 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704286
Three-dimensional memory device with self-aligned multi-level drain select gate electrodes Sep 13, 2017 Issued
Array ( [id] => 14177951 [patent_doc_number] => 10262997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => High-voltage LDMOSFET devices having polysilicon trench-type guard rings [patent_app_type] => utility [patent_app_number] => 15/704375 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4271 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704375 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704375
High-voltage LDMOSFET devices having polysilicon trench-type guard rings Sep 13, 2017 Issued
Array ( [id] => 13435351 [patent_doc_number] => 20180269218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/704667 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704667
Semiconductor memory device with floating gates having a curved lateral surface Sep 13, 2017 Issued
Array ( [id] => 12759694 [patent_doc_number] => 20180145066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => ESD PROTECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/704459 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704459
ESD PROTECTION CIRCUIT Sep 13, 2017 Abandoned
Array ( [id] => 14050079 [patent_doc_number] => 20190081147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => MOSFET WITH VERTICAL VARIATION OF GATE-PILLAR SEPARATION [patent_app_type] => utility [patent_app_number] => 15/703699 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703699 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703699
MOSFET WITH VERTICAL VARIATION OF GATE-PILLAR SEPARATION Sep 12, 2017 Abandoned
Array ( [id] => 12263938 [patent_doc_number] => 20180083133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'NORMALLY-OFF, CUBIC PHASE GALLIUM NITRIDE (GAN) FIELD-EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/703850 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9486 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703850
Normally-off cubic phase GaN (c-GaN) HEMT having a gate electrode dielectrically insulated from a c-AlGaN capping layer Sep 12, 2017 Issued
Array ( [id] => 12263958 [patent_doc_number] => 20180083154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/703525 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9642 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703525
Germanium-based photoreceiver having tungsten contacts Sep 12, 2017 Issued
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