Search

Anna L. Verderame

Examiner (ID: 19741)

Most Active Art Unit
1795
Art Unit(s)
1722, 1756, 1795
Total Applications
250
Issued Applications
70
Pending Applications
1
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11974634 [patent_doc_number] => 20170278788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION' [patent_app_type] => utility [patent_app_number] => 15/479983 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479983 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/479983
Interconnect structure including air gaps enclosed between conductive lines and a permeable dielectric layer Apr 4, 2017 Issued
Array ( [id] => 13909703 [patent_doc_number] => 20190044056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MAGNETIC TUNNEL JUNCTION STRUCTURE WITH PERPENDICULAR MAGNETIC ANISOTROPY AND MAGNETIC ELEMENT INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/087445 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6087 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087445
Magnetic tunnel junction (MTJ) structure with perpendicular magnetic anisotropy (PMA) having an oxide-based PMA-inducing layer and magnetic element including the same Mar 21, 2017 Issued
Array ( [id] => 13214821 [patent_doc_number] => 10121786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers [patent_app_type] => utility [patent_app_number] => 15/464213 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 7351 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15464213 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/464213
FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers Mar 19, 2017 Issued
Array ( [id] => 16739068 [patent_doc_number] => 10964735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Solid-state imaging device having pixels with high and low sensitivity photoelectric conversion units, and electronic device including the same [patent_app_type] => utility [patent_app_number] => 16/087131 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 64 [patent_no_of_words] => 28117 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087131
Solid-state imaging device having pixels with high and low sensitivity photoelectric conversion units, and electronic device including the same Mar 14, 2017 Issued
Array ( [id] => 16739068 [patent_doc_number] => 10964735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Solid-state imaging device having pixels with high and low sensitivity photoelectric conversion units, and electronic device including the same [patent_app_type] => utility [patent_app_number] => 16/087131 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 64 [patent_no_of_words] => 28117 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087131
Solid-state imaging device having pixels with high and low sensitivity photoelectric conversion units, and electronic device including the same Mar 14, 2017 Issued
Array ( [id] => 16739068 [patent_doc_number] => 10964735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Solid-state imaging device having pixels with high and low sensitivity photoelectric conversion units, and electronic device including the same [patent_app_type] => utility [patent_app_number] => 16/087131 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 64 [patent_no_of_words] => 28117 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087131
Solid-state imaging device having pixels with high and low sensitivity photoelectric conversion units, and electronic device including the same Mar 14, 2017 Issued
Array ( [id] => 16739068 [patent_doc_number] => 10964735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Solid-state imaging device having pixels with high and low sensitivity photoelectric conversion units, and electronic device including the same [patent_app_type] => utility [patent_app_number] => 16/087131 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 64 [patent_no_of_words] => 28117 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087131
Solid-state imaging device having pixels with high and low sensitivity photoelectric conversion units, and electronic device including the same Mar 14, 2017 Issued
Array ( [id] => 11710595 [patent_doc_number] => 20170179093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Inter-Chip Alignment' [patent_app_type] => utility [patent_app_number] => 15/448026 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5229 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15448026 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/448026
Quilt packaging system with mated metal interconnect nodules and voids Mar 1, 2017 Issued
Array ( [id] => 14164347 [patent_doc_number] => 20190109276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => MAGNETORESISTIVE ELEMENT, MEMORY ELEMENT, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/087206 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087206
MAGNETORESISTIVE ELEMENT, MEMORY ELEMENT, AND ELECTRONIC APPARATUS Feb 20, 2017 Abandoned
Array ( [id] => 14138223 [patent_doc_number] => 20190103501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => LIGHT-RECEIVING DEVICE, IMAGING UNIT, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/087189 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087189 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087189
LIGHT-RECEIVING DEVICE, IMAGING UNIT, AND ELECTRONIC APPARATUS Feb 14, 2017 Abandoned
Array ( [id] => 16645663 [patent_doc_number] => 10923531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Nonvolatile memory device having an oxidized magnetic material film around a magnetic material layer and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/087177 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6907 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16087177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/087177
Nonvolatile memory device having an oxidized magnetic material film around a magnetic material layer and method of manufacturing the same Feb 7, 2017 Issued
Array ( [id] => 13283221 [patent_doc_number] => 10153201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Method for making a dipole-based contact structure to reduce the metal-semiconductor contact resistance in MOSFETs [patent_app_type] => utility [patent_app_number] => 15/417848 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 4024 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417848 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417848
Method for making a dipole-based contact structure to reduce the metal-semiconductor contact resistance in MOSFETs Jan 26, 2017 Issued
Array ( [id] => 11760396 [patent_doc_number] => 20170207265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'METHOD OF MANUFACTURING AN ELECTROMAGNETIC RADIATION DETECTOR WITH MICRO-ENCAPSULATION' [patent_app_type] => utility [patent_app_number] => 15/400278 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19651 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400278 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400278
Method of manufacturing an infrared detector having a micro-cavity and a low refraction index step at an interface with a transparent cap, and associated infrared detector Jan 5, 2017 Issued
Array ( [id] => 12918436 [patent_doc_number] => 20180197988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => MULTI-GATE VERTICAL FIELD EFFECT TRANSISTOR WITH CHANNEL STRIPS LATERALLY CONFINED BY GATE DIELECTRIC LAYERS, AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 15/400244 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400244 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400244
Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof Jan 5, 2017 Issued
Array ( [id] => 13070951 [patent_doc_number] => 10056260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Schottky diode with dielectrically isolated diffusions, and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/398999 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3104 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398999 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/398999
Schottky diode with dielectrically isolated diffusions, and method of manufacturing the same Jan 4, 2017 Issued
Array ( [id] => 13057457 [patent_doc_number] => 10050130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Method of fabricating a semiconductor structure by asymmetric oxidation of fin material formed under gate stack [patent_app_type] => utility [patent_app_number] => 15/398817 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398817 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/398817
Method of fabricating a semiconductor structure by asymmetric oxidation of fin material formed under gate stack Jan 4, 2017 Issued
Array ( [id] => 11732814 [patent_doc_number] => 20170194257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'METHOD FOR THE MANUFACTURE OF METAL STRUCTURES AND AN ELECTRONIC COMPONENT WITH AT LEAST ONE METAL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/399286 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4602 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399286
Method for manufacturing a contact bump by thermal expansion of a patterned sacrificial layer underneath a galvanic layer Jan 4, 2017 Issued
Array ( [id] => 12896200 [patent_doc_number] => 20180190575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => LEADFRAME WITH LEAD PROTRUDING FROM THE PACKAGE [patent_app_type] => utility [patent_app_number] => 15/399536 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399536
LEADFRAME WITH LEAD PROTRUDING FROM THE PACKAGE Jan 4, 2017 Abandoned
Array ( [id] => 14459855 [patent_doc_number] => 10325901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-18 [patent_title] => Circuit for increasing the impedance of an ESD path in an input/output circuit and method of implementing the same [patent_app_type] => utility [patent_app_number] => 15/399672 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3742 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399672 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399672
Circuit for increasing the impedance of an ESD path in an input/output circuit and method of implementing the same Jan 4, 2017 Issued
Array ( [id] => 12779716 [patent_doc_number] => 20180151740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => Methods for Straining a Transistor Gate through Interlayer Dielectric (ILD) Doping Schemes [patent_app_type] => utility [patent_app_number] => 15/399241 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399241 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399241
Methods for straining a transistor gate through interlayer dielectric (ILD) doping schemes Jan 4, 2017 Issued
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