Search

Anna L. Verderame

Examiner (ID: 19741)

Most Active Art Unit
1795
Art Unit(s)
1722, 1756, 1795
Total Applications
250
Issued Applications
70
Pending Applications
1
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13921475 [patent_doc_number] => 10204861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Structure with local contact for shorting a gate electrode to a source/drain region [patent_app_type] => utility [patent_app_number] => 15/399200 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4069 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399200 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399200
Structure with local contact for shorting a gate electrode to a source/drain region Jan 4, 2017 Issued
Array ( [id] => 16067699 [patent_doc_number] => 10692813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Semiconductor package with dummy bumps connected to non-solder mask defined pads [patent_app_type] => utility [patent_app_number] => 15/398724 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398724 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/398724
Semiconductor package with dummy bumps connected to non-solder mask defined pads Jan 4, 2017 Issued
Array ( [id] => 12162474 [patent_doc_number] => 20180033740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'Dummy Fin Etch to Form Recesses in Substrate' [patent_app_type] => utility [patent_app_number] => 15/399237 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399237 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399237
Integrated circuit structure having crown-shaped semiconductor strips and recesses in the substrate from etched dummy fins Jan 4, 2017 Issued
Array ( [id] => 12554361 [patent_doc_number] => 10014345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-03 [patent_title] => Magnetic memory device with grid-shaped common source plate, system, and method of fabrication [patent_app_type] => utility [patent_app_number] => 15/399509 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 8229 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399509
Magnetic memory device with grid-shaped common source plate, system, and method of fabrication Jan 4, 2017 Issued
Array ( [id] => 12554442 [patent_doc_number] => 10014372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-03 [patent_title] => Vertical gate-all-around transistor with top and bottom source/drain epitaxy on a replacement nanowire, and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/399064 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399064 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399064
Vertical gate-all-around transistor with top and bottom source/drain epitaxy on a replacement nanowire, and method of manufacturing the same Jan 4, 2017 Issued
Array ( [id] => 11746654 [patent_doc_number] => 20170200727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 15/399243 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399243 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399243
Anti-fuse one-time programmable (OTP) device Jan 4, 2017 Issued
Array ( [id] => 13145951 [patent_doc_number] => 10090315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Semiconductor memory device in which an array chip including three-dimensionally disposed memory cells bonded to a control circuit chip [patent_app_type] => utility [patent_app_number] => 15/388318 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6275 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15388318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/388318
Semiconductor memory device in which an array chip including three-dimensionally disposed memory cells bonded to a control circuit chip Dec 21, 2016 Issued
Array ( [id] => 13043489 [patent_doc_number] => 10043887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Methods for forming a semiconductor device with a gate stack having angled sidewalls [patent_app_type] => utility [patent_app_number] => 15/376610 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376610 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/376610
Methods for forming a semiconductor device with a gate stack having angled sidewalls Dec 11, 2016 Issued
Array ( [id] => 11517415 [patent_doc_number] => 20170084489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Device with Through-Substrate Via Structure and Method for Forming the Same' [patent_app_type] => utility [patent_app_number] => 15/369409 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15369409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/369409
Methods for forming a device having a capped through-substrate via structure Dec 4, 2016 Issued
Array ( [id] => 11517420 [patent_doc_number] => 20170084494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'MULTI-DEPTH ETCHING IN SEMICONDUCTOR ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 15/368786 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15368786 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/368786
Methods for forming a semiconductor arrangement with multiple-height fins and substrate trenches Dec 4, 2016 Issued
Array ( [id] => 13996389 [patent_doc_number] => 20190067352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => PHOTOSENSITIVE CHIP PACKAGING STRUCTURE AND PACKAGING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/766781 [patent_app_country] => US [patent_app_date] => 2016-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15766781 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/766781
PHOTOSENSITIVE CHIP PACKAGING STRUCTURE AND PACKAGING METHOD THEREOF Oct 27, 2016 Abandoned
Array ( [id] => 14036449 [patent_doc_number] => 10229981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrate [patent_app_type] => utility [patent_app_number] => 15/335281 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 36 [patent_no_of_words] => 9329 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/335281
Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrate Oct 25, 2016 Issued
Array ( [id] => 16035193 [patent_doc_number] => 10680030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Image sensing device having a junction capacity expansion structure [patent_app_type] => utility [patent_app_number] => 15/771516 [patent_app_country] => US [patent_app_date] => 2016-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 39 [patent_no_of_words] => 12683 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15771516 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/771516
Image sensing device having a junction capacity expansion structure Oct 20, 2016 Issued
Array ( [id] => 12478011 [patent_doc_number] => 09991258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator [patent_app_type] => utility [patent_app_number] => 15/292768 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3601 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292768 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/292768
FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator Oct 12, 2016 Issued
Array ( [id] => 13996385 [patent_doc_number] => 20190067350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => IMAGE PICKUP ELEMENT PACKAGE, IMAGE PICKUP APPARATUS, AND MANUFACTURING METHOD FOR AN IMAGE PICKUP ELEMENT PACKAGE [patent_app_type] => utility [patent_app_number] => 15/773617 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15773617 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/773617
Image pickup element package having a supporting resin frame with a thermally conductive portion including electronic components, and associated image pickup apparatus Oct 6, 2016 Issued
Array ( [id] => 12954067 [patent_doc_number] => 09837503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Transistor having metal electrodes surrounding a semiconductor pillar body and corresponding work-function-induced source/drain regions [patent_app_type] => utility [patent_app_number] => 15/287102 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2976 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/287102
Transistor having metal electrodes surrounding a semiconductor pillar body and corresponding work-function-induced source/drain regions Oct 5, 2016 Issued
Array ( [id] => 11503038 [patent_doc_number] => 20170077223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 15/273951 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5943 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273951
FET with local isolation layers on S/D trench sidewalls Sep 22, 2016 Issued
Array ( [id] => 11353798 [patent_doc_number] => 20160372538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'Method of Manufacturing a Semiconductor Device Having a Charge Compensation Region Underneath a Gate Trench' [patent_app_type] => utility [patent_app_number] => 15/251606 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7235 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15251606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/251606
Method of manufacturing a semiconductor device having a charge compensation region underneath a gate trench Aug 29, 2016 Issued
Array ( [id] => 12229771 [patent_doc_number] => 09917020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Methods for fabricating an integrated circuit having vertically overlapping short and long channel FinFETs' [patent_app_type] => utility [patent_app_number] => 15/238559 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 4352 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238559 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238559
Methods for fabricating an integrated circuit having vertically overlapping short and long channel FinFETs Aug 15, 2016 Issued
Array ( [id] => 12554082 [patent_doc_number] => 10014252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors [patent_app_type] => utility [patent_app_number] => 15/201122 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201122 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201122
Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors Jun 30, 2016 Issued
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