Anna L. Verderame

Array ( [id] => 11194394 [patent_doc_number] => 09425213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-23 [patent_title] => 'Stacked short and long channel FinFETs' [patent_app_type] => utility [patent_app_number] => 14/788341 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 37 [patent_no_of_words] => 4354 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11564783 [patent_doc_number] => 09627378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding' [patent_app_type] => utility [patent_app_number] => 14/788297 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 7548 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12334932 [patent_doc_number] => 09947645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Multi-project wafer with IP protection by reticle mask pattern modification [patent_app_type] => utility [patent_app_number] => 14/751170 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 6320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10410056 [patent_doc_number] => 20150295065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES' [patent_app_type] => utility [patent_app_number] => 14/752095 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3591 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11802420 [patent_doc_number] => 09543322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Methods for producing a thin film ferroelectric device using a two-step temperature process on an organic polymeric ferroelectric precursor material stacked between two conductive materials' [patent_app_type] => utility [patent_app_number] => 14/902114 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 12164 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14902114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10378158 [patent_doc_number] => 20150263165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'Semiconductor Device Having a Charge Compensation Region' [patent_app_type] => utility [patent_app_number] => 14/727420 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6166 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10402770 [patent_doc_number] => 20150287779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH TALL FINS AND USING HARD MASK ETCH STOPS' [patent_app_type] => utility [patent_app_number] => 14/726282 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12109196 [patent_doc_number] => 09865684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Nanoscale structure with epitaxial film having a recessed bottom portion' [patent_app_type] => utility [patent_app_number] => 14/707292 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14707292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11279876 [patent_doc_number] => 09496360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Vertical transistor with source/drain regions induced by work-function differences between a semiconductor pillar body and surrounding metal electrodes' [patent_app_type] => utility [patent_app_number] => 14/680167 [patent_app_country] => US [patent_app_date] => 2015-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2880 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14680167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10351099 [patent_doc_number] => 20150236105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTORS HAVING A SURROUNDING GATE AND A WORK-FUNCTION METAL AROUND AN UPPER SIDEWALL' [patent_app_type] => utility [patent_app_number] => 14/672448 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 6735 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12574125 [patent_doc_number] => 10020303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Methods for forming FinFETs having epitaxial Si S/D extensions with flat top surfaces on a SiGe seed layer [patent_app_type] => utility [patent_app_number] => 14/666464 [patent_app_country] => US [patent_app_date] => 2015-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3627 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14666464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10395014 [patent_doc_number] => 20150280022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'SURFACE PREPARATION AND UNIFORM PLATING ON THROUGH WAFER VIAS AND INTERCONNECTS FOR PHOTOVOLTAICS' [patent_app_type] => utility [patent_app_number] => 14/663115 [patent_app_country] => US [patent_app_date] => 2015-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8654 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14663115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12478002 [patent_doc_number] => 09991255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces [patent_app_type] => utility [patent_app_number] => 14/661590 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3582 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14661590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11918573 [patent_doc_number] => 09786766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Methods of fabricating transistors with a protection layer to improve the insulation between a gate electrode and a junction region' [patent_app_type] => utility [patent_app_number] => 14/643695 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2767 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14643695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12396381 [patent_doc_number] => 09966384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Methods of manufacturing a semiconductor device with non-overlapping slits in-between memory blocks [patent_app_type] => utility [patent_app_number] => 14/623943 [patent_app_country] => US [patent_app_date] => 2015-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 7588 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14623943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10409997 [patent_doc_number] => 20150295006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'LIGHT SENSING DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/554072 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4824 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11599987 [patent_doc_number] => 09647166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Electronic device including laterally arranged P-type and N-type regions in a two dimensional (2D) material layer and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/554363 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4021 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10744147 [patent_doc_number] => 20160090298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'PACKAGES FOR STRESS-SENSITIVE DEVICE DIES' [patent_app_type] => utility [patent_app_number] => 14/554661 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6438 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11253140 [patent_doc_number] => 09478656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Method for fabricating a field effect transistor with local isolations on raised source/drain trench sidewalls' [patent_app_type] => utility [patent_app_number] => 14/554168 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5938 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10425904 [patent_doc_number] => 20150310915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'Memory Cell Retention Enhancement Through Erase State Modification' [patent_app_type] => utility [patent_app_number] => 14/554383 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2191 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554383 [rel_patent_id] =>[rel_patent_doc_number] =>)