Search

Anna L. Verderame

Examiner (ID: 19741)

Most Active Art Unit
1795
Art Unit(s)
1722, 1756, 1795
Total Applications
250
Issued Applications
70
Pending Applications
1
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11599721 [patent_doc_number] => 09646898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Methods for treating a substrate by optical projection of a correction pattern based on a detected spatial heat signature of the substrate' [patent_app_type] => utility [patent_app_number] => 14/554358 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6957 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554358 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554358
Methods for treating a substrate by optical projection of a correction pattern based on a detected spatial heat signature of the substrate Nov 25, 2014 Issued
Array ( [id] => 11214932 [patent_doc_number] => 09443973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Semiconductor device with charge compensation region underneath gate trench' [patent_app_type] => utility [patent_app_number] => 14/554193 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7234 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 470 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554193 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554193
Semiconductor device with charge compensation region underneath gate trench Nov 25, 2014 Issued
Array ( [id] => 11776193 [patent_doc_number] => 09385145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Double thin film transistor structure with shared gate' [patent_app_type] => utility [patent_app_number] => 14/554104 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4677 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554104 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554104
Double thin film transistor structure with shared gate Nov 25, 2014 Issued
Array ( [id] => 10329100 [patent_doc_number] => 20150214103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/549789 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549789 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549789
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Nov 20, 2014 Abandoned
Array ( [id] => 11096681 [patent_doc_number] => 20160293650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'IMAGE PICKUP DEVICE' [patent_app_type] => utility [patent_app_number] => 15/024146 [patent_app_country] => US [patent_app_date] => 2014-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15024146 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/024146
Image pickup device having an infrared absorption layer between a laminate band-pass layer and a low refractive index layer above on-chip lenses Nov 19, 2014 Issued
Array ( [id] => 10296733 [patent_doc_number] => 20150181733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'THREE-DIMENSIONAL PACKAGE STRUCTURE AND THE METHOD TO FABRICATE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/536699 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4825 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14536699 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/536699
Three-dimensional (3D) package structure with electronic components encapsulated by a connection structure over an inductor Nov 9, 2014 Issued
Array ( [id] => 10378016 [patent_doc_number] => 20150263023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/529851 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8393 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14529851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/529851
NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME Oct 30, 2014 Abandoned
Array ( [id] => 10237321 [patent_doc_number] => 20150122315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'TWO-DIMENSIONAL MATERIALS, METHODS OF FORMING THE SAME, AND DEVICES INCLUDING TWO-DIMENSIONAL MATERIALS' [patent_app_type] => utility [patent_app_number] => 14/508378 [patent_app_country] => US [patent_app_date] => 2014-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16034 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14508378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/508378
Two-dimensional (2D) material element with in-plane metal chalcogenide-based heterojunctions and devices including said element Oct 6, 2014 Issued
Array ( [id] => 10597370 [patent_doc_number] => 09318466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Method for electronic circuit assembly on a paper substrate' [patent_app_type] => utility [patent_app_number] => 14/471620 [patent_app_country] => US [patent_app_date] => 2014-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3530 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14471620 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/471620
Method for electronic circuit assembly on a paper substrate Aug 27, 2014 Issued
Array ( [id] => 10336577 [patent_doc_number] => 20150221582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'CONNECTOR FRAME AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/456722 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5728 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456722 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/456722
CONNECTOR FRAME AND SEMICONDUCTOR DEVICE Aug 10, 2014 Abandoned
Array ( [id] => 10696946 [patent_doc_number] => 20160043093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/456496 [patent_app_country] => US [patent_app_date] => 2014-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9847 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456496 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/456496
Three dimensional NAND string memory devices with voids enclosed between control gate electrodes Aug 10, 2014 Issued
Array ( [id] => 10696950 [patent_doc_number] => 20160043097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SELF-ALIGNED SPLIT GATE FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 14/454872 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6650 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454872 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454872
Self-aligned split gate flash memory having liner-separated spacers above the memory gate Aug 7, 2014 Issued
Array ( [id] => 9905875 [patent_doc_number] => 20150061075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'METAL TRENCH DE-COUPLING CAPACITOR STRUCTURE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/453625 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4207 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453625 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/453625
Metal trench decoupling capacitor structure penetrating through a shallow trench isolation Aug 6, 2014 Issued
Array ( [id] => 9861976 [patent_doc_number] => 20150041994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'SEMICONDUCTOR PACKAGE HAVING RECESSED SOLDER TERMINALS' [patent_app_type] => utility [patent_app_number] => 14/453650 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4122 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453650 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/453650
Semiconductor package with lead frame and recessed solder terminals Aug 6, 2014 Issued
Array ( [id] => 10252255 [patent_doc_number] => 20150137251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/454476 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454476 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454476
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 6, 2014 Abandoned
Array ( [id] => 11911219 [patent_doc_number] => 09780040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Integrated circuit package substrates having a common die dependent region and methods for designing the same' [patent_app_type] => utility [patent_app_number] => 14/454115 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4882 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14454115 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/454115
Integrated circuit package substrates having a common die dependent region and methods for designing the same Aug 6, 2014 Issued
Array ( [id] => 10230404 [patent_doc_number] => 20150115398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/453310 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453310 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/453310
Methods of manufacturing semiconductor devices including capped metal patterns with air gaps in-between for parasitic capacitance reduction Aug 5, 2014 Issued
Array ( [id] => 10277446 [patent_doc_number] => 20150162443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SEMICONDUCTOR POWER DEVICES AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/452730 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452730 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/452730
SEMICONDUCTOR POWER DEVICES AND METHODS OF MANUFACTURING THE SAME Aug 5, 2014 Abandoned
Array ( [id] => 10518942 [patent_doc_number] => 09245997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Method of fabricating a LDMOS device having a first well depth less than a second well depth' [patent_app_type] => utility [patent_app_number] => 14/453246 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8298 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453246 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/453246
Method of fabricating a LDMOS device having a first well depth less than a second well depth Aug 5, 2014 Issued
Array ( [id] => 9861963 [patent_doc_number] => 20150041980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'Semiconductor Package with Reduced Thickness' [patent_app_type] => utility [patent_app_number] => 14/452933 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452933 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/452933
Semiconductor Package with Reduced Thickness Aug 5, 2014 Abandoned
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