Search

Anna L. Verderame

Examiner (ID: 19741)

Most Active Art Unit
1795
Art Unit(s)
1722, 1756, 1795
Total Applications
250
Issued Applications
70
Pending Applications
1
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19086359 [patent_doc_number] => 20240113160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/303205 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303205
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Apr 18, 2023 Pending
Array ( [id] => 18743594 [patent_doc_number] => 20230352582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => POWER TRANSISTOR DEVICE AND METHOD OF FABRICATING A TRANSISTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/135788 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135788 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135788
Power transistor device having an interfacial silicon nitride layer between a field plate and a substrate region and method of fabricating the same Apr 17, 2023 Issued
Array ( [id] => 20760211 [patent_doc_number] => 12653006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Semiconductor device including isolation structures doped with impurities and having charge trapping layers [patent_app_type] => utility [patent_app_number] => 18/135339 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 3170 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135339
Semiconductor device including isolation structures doped with impurities and having charge trapping layers Apr 16, 2023 Issued
Array ( [id] => 19886903 [patent_doc_number] => 12272634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor structure having an anchor-shaped backside via [patent_app_type] => utility [patent_app_number] => 18/301757 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 40 [patent_no_of_words] => 10273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301757 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301757
Semiconductor structure having an anchor-shaped backside via Apr 16, 2023 Issued
Array ( [id] => 19452916 [patent_doc_number] => 20240313046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/134555 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134555
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Apr 12, 2023 Pending
Array ( [id] => 18833850 [patent_doc_number] => 20230402377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/120845 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120845
SEMICONDUCTOR DEVICES Mar 12, 2023 Pending
Array ( [id] => 18712925 [patent_doc_number] => 20230335558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/117891 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18117891 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/117891
SEMICONDUCTOR DEVICE Mar 5, 2023 Pending
Array ( [id] => 19191426 [patent_doc_number] => 20240170339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/116713 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18116713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/116713
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE Mar 1, 2023 Issued
Array ( [id] => 18927310 [patent_doc_number] => 20240030314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/175176 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175176 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175176
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Feb 26, 2023 Pending
Array ( [id] => 18833787 [patent_doc_number] => 20230402314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/173948 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/173948
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Feb 23, 2023 Pending
Array ( [id] => 18679938 [patent_doc_number] => 20230317596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/107070 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107070
Semiconductor device having a source/drain contact connected to a back-side power rail by a landing pad and a through electrode Feb 7, 2023 Issued
Array ( [id] => 19364183 [patent_doc_number] => 20240266217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SELF-ALIGNED SMALL CONTACT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/166403 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166403 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166403
Self-aligned source/drain contact structure and method of manufacturing the same Feb 7, 2023 Issued
Array ( [id] => 18396788 [patent_doc_number] => 20230165009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/100613 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100613
Semiconductor memory device having a contact plug electrically connected to an interconnection through a narrower via Jan 23, 2023 Issued
Array ( [id] => 18379699 [patent_doc_number] => 20230154788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH PROTECTION CAP [patent_app_type] => utility [patent_app_number] => 18/154540 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154540 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154540
Semiconductor device structure with a protection cap at an end portion of a conductive line Jan 12, 2023 Issued
Array ( [id] => 20484201 [patent_doc_number] => 12532682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Method of manufacturing a structure by asymmetrical ion bombardment of a capped underlying layer [patent_app_type] => utility [patent_app_number] => 18/096980 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 0 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096980
Method of manufacturing a structure by asymmetrical ion bombardment of a capped underlying layer Jan 12, 2023 Issued
Array ( [id] => 18409035 [patent_doc_number] => 20230170388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => CMOS FINFET DEVICE HAVING STRAINED SIGE FINS AND A STRAINED SI CLADDING LAYER ON THE NMOS CHANNEL [patent_app_type] => utility [patent_app_number] => 18/095720 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095720 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095720
CMOS FINFET DEVICE HAVING STRAINED SIGE FINS AND A STRAINED SI CLADDING LAYER ON THE NMOS CHANNEL Jan 10, 2023 Abandoned
Array ( [id] => 18365822 [patent_doc_number] => 20230147413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => Via Structures [patent_app_type] => utility [patent_app_number] => 18/149265 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149265
Via Structures Jan 2, 2023 Pending
Array ( [id] => 19705122 [patent_doc_number] => 12199170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Method of manufacturing a multi-gate device having a semiconductor seed layer embedded in an isolation layer [patent_app_type] => utility [patent_app_number] => 18/066373 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066373 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066373
Method of manufacturing a multi-gate device having a semiconductor seed layer embedded in an isolation layer Dec 14, 2022 Issued
Array ( [id] => 20260591 [patent_doc_number] => 12432962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => FinFET device with source/drain contact extending over dielectric gate [patent_app_type] => utility [patent_app_number] => 18/064785 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 3481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064785
FinFET device with source/drain contact extending over dielectric gate Dec 11, 2022 Issued
Array ( [id] => 20245971 [patent_doc_number] => 12426316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material [patent_app_type] => utility [patent_app_number] => 17/993438 [patent_app_country] => US [patent_app_date] => 2022-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 36 [patent_no_of_words] => 9621 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17993438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/993438
Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material Nov 22, 2022 Issued
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