Search

Anna Pagonakis

Examiner (ID: 9388, Phone: (571)270-3505 , Office: P/1628 )

Most Active Art Unit
1628
Art Unit(s)
6221, 1609, 1628, OPET, 4173, 1614
Total Applications
1249
Issued Applications
445
Pending Applications
84
Abandoned Applications
723

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16432992 [patent_doc_number] => 10833089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Buried conductive layer supplying digital circuits [patent_app_type] => utility [patent_app_number] => 16/192992 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 10954 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192992
Buried conductive layer supplying digital circuits Nov 15, 2018 Issued
Array ( [id] => 15580945 [patent_doc_number] => 10580867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance [patent_app_type] => utility [patent_app_number] => 16/192930 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 8436 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192930 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192930
FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance Nov 15, 2018 Issued
Array ( [id] => 15611341 [patent_doc_number] => 10586740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Method for manufacturing pairs of CMOS transistors of the "fin-FET" type at low temperatures [patent_app_type] => utility [patent_app_number] => 16/191951 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 6107 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16191951 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/191951
Method for manufacturing pairs of CMOS transistors of the "fin-FET" type at low temperatures Nov 14, 2018 Issued
Array ( [id] => 14310605 [patent_doc_number] => 20190145006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 16/190834 [patent_app_country] => US [patent_app_date] => 2018-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16190834 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/190834
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium Nov 13, 2018 Issued
Array ( [id] => 15260491 [patent_doc_number] => 20190378979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => METHOD OF MANUFACTURING ORGANIC SEMICONDUCTOR THIN FILM USING BAR-COATING PROCESS AND METHOD OF FABRICATING FLEXIBLE ORGANIC SEMICONDUCTOR TRANSISTOR COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 16/189897 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189897
Method of manufacturing organic semiconductor thin film using bar-coating process and method of fabricating flexible organic semiconductor transistor comprising the same Nov 12, 2018 Issued
Array ( [id] => 15375749 [patent_doc_number] => 10529602 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Method and apparatus for substrate fabrication [patent_app_type] => utility [patent_app_number] => 16/189487 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189487 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189487
Method and apparatus for substrate fabrication Nov 12, 2018 Issued
Array ( [id] => 15922005 [patent_doc_number] => 10658250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Light irradiation type heat treatment method and heat treatment apparatus [patent_app_type] => utility [patent_app_number] => 16/188672 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11930 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16188672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/188672
Light irradiation type heat treatment method and heat treatment apparatus Nov 12, 2018 Issued
Array ( [id] => 15673019 [patent_doc_number] => 10600750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Interconnect structures for preventing solder bridging, and associated systems and methods [patent_app_type] => utility [patent_app_number] => 16/182924 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/182924
Interconnect structures for preventing solder bridging, and associated systems and methods Nov 6, 2018 Issued
Array ( [id] => 15375863 [patent_doc_number] => 10529659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Semiconductor devices having electrically and optically conductive vias, and associated systems and methods [patent_app_type] => utility [patent_app_number] => 16/182901 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182901 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/182901
Semiconductor devices having electrically and optically conductive vias, and associated systems and methods Nov 6, 2018 Issued
Array ( [id] => 15733303 [patent_doc_number] => 10615085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Method for predicting thickness of oxide layer of silicon wafer [patent_app_type] => utility [patent_app_number] => 16/172947 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3080 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16172947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/172947
Method for predicting thickness of oxide layer of silicon wafer Oct 28, 2018 Issued
Array ( [id] => 13963241 [patent_doc_number] => 20190057965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => FINFET AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/167554 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/167554
FinFET and manufacturing method of the same Oct 22, 2018 Issued
Array ( [id] => 15286861 [patent_doc_number] => 10516102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => Multiple spacer assisted physical etching of sub 60nm MRAM devices [patent_app_type] => utility [patent_app_number] => 16/161139 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2305 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16161139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/161139
Multiple spacer assisted physical etching of sub 60nm MRAM devices Oct 15, 2018 Issued
Array ( [id] => 13847785 [patent_doc_number] => 20190027377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/130546 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130546 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/130546
Semiconductor device and manufacturing method thereof Sep 12, 2018 Issued
Array ( [id] => 14046277 [patent_doc_number] => 20190079245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => Deterministic Frequency Tuning of Quantum Dots in Photonic Crystal Membranes Using Micro-Laser Processing [patent_app_type] => utility [patent_app_number] => 16/127873 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127873 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/127873
Deterministic frequency tuning of quantum dots in photonic crystal membranes using micro-laser processing Sep 10, 2018 Issued
Array ( [id] => 15061917 [patent_doc_number] => 10461271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Light-emitting element, display device, electronic device, and lighting device [patent_app_type] => utility [patent_app_number] => 16/113128 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 73 [patent_no_of_words] => 43461 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16113128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/113128
Light-emitting element, display device, electronic device, and lighting device Aug 26, 2018 Issued
Array ( [id] => 15676687 [patent_doc_number] => 10602608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Circuit board [patent_app_type] => utility [patent_app_number] => 16/107233 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7249 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107233 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107233
Circuit board Aug 20, 2018 Issued
Array ( [id] => 15565131 [patent_doc_number] => 20200066977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => PHASE CHANGE MEMORY WITH A DIELECTRIC BI-LAYER [patent_app_type] => utility [patent_app_number] => 16/107323 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107323
Phase change memory with a dielectric bi-layer Aug 20, 2018 Issued
Array ( [id] => 16308778 [patent_doc_number] => 10777588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Method of fabricating thin film transistor, thin film transistor, array substrate, and display apparatus [patent_app_type] => utility [patent_app_number] => 16/341012 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6404 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16341012 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/341012
Method of fabricating thin film transistor, thin film transistor, array substrate, and display apparatus Aug 12, 2018 Issued
Array ( [id] => 13598435 [patent_doc_number] => 20180350766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE [patent_app_type] => utility [patent_app_number] => 16/058425 [patent_app_country] => US [patent_app_date] => 2018-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16058425 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/058425
Package-on-package assembly with wire bonds to encapsulation surface Aug 7, 2018 Issued
Array ( [id] => 13996307 [patent_doc_number] => 20190067311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/057648 [patent_app_country] => US [patent_app_date] => 2018-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057648
Memory device and method for manufacturing memory device Aug 6, 2018 Issued
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