Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9410374 [patent_doc_number] => 20140101626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS' [patent_app_type] => utility [patent_app_number] => 14/101448 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101448 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/101448
System and method of electromigration mitigation in stacked IC designs Dec 9, 2013 Issued
Array ( [id] => 9365529 [patent_doc_number] => 20140075402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'Method of Fast Analog Layout Migration' [patent_app_type] => utility [patent_app_number] => 14/082885 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4811 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082885 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082885
Method of fast analog layout migration Nov 17, 2013 Issued
Array ( [id] => 10406035 [patent_doc_number] => 20150291044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'CHARGE-DISCHARGE MANAGEMENT DEVICE, POWER CONDITIONER, POWER STORAGE DEVICE, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/441624 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7806 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14441624 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/441624
CHARGE-DISCHARGE MANAGEMENT DEVICE, POWER CONDITIONER, POWER STORAGE DEVICE, AND PROGRAM Nov 12, 2013 Abandoned
Array ( [id] => 10410441 [patent_doc_number] => 20150295450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'WIRELESS POWER RECEIVING DEVICE AND POWER CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/441791 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14441791 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/441791
Wireless power receiving device and power control method thereof Nov 5, 2013 Issued
Array ( [id] => 9540374 [patent_doc_number] => 20140165021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'SYSTEM AND METHODS FOR DYNAMIC MANAGEMENT OF HARDWARE RESOURCES' [patent_app_type] => utility [patent_app_number] => 14/069822 [patent_app_country] => US [patent_app_date] => 2013-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9796 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14069822 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/069822
System and methods for dynamic management of hardware resources Oct 31, 2013 Issued
Array ( [id] => 13668519 [patent_doc_number] => 10164446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Discharge circuit malfunction diagnosis device and discharge circuit malfunction diagnosis method [patent_app_type] => utility [patent_app_number] => 14/917412 [patent_app_country] => US [patent_app_date] => 2013-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7013 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917412 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/917412
Discharge circuit malfunction diagnosis device and discharge circuit malfunction diagnosis method Oct 28, 2013 Issued
Array ( [id] => 9474404 [patent_doc_number] => 20140131867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR PACKAGE USING COMPUTING SYSTEM, APPARATUS FOR FABRICATING SEMICONDUCTOR PACKAGE INCLUDING THE SYSTEM, AND SEMICONDUCTOR PACKAGE DESIGNED BY THE METHOD' [patent_app_type] => utility [patent_app_number] => 14/064102 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9482 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064102 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064102
System and method for designing semiconductor package using computing system, apparatus for fabricating semiconductor package including the system, and semiconductor package designed by the method Oct 24, 2013 Issued
Array ( [id] => 9980647 [patent_doc_number] => 09026978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-05 [patent_title] => 'Reverse interface logic model for optimizing physical hierarchy under full chip constraint' [patent_app_type] => utility [patent_app_number] => 14/062807 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14062807 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/062807
Reverse interface logic model for optimizing physical hierarchy under full chip constraint Oct 23, 2013 Issued
Array ( [id] => 9297207 [patent_doc_number] => 20140040841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 14/047396 [patent_app_country] => US [patent_app_date] => 2013-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3330 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14047396 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/047396
Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design Oct 6, 2013 Issued
Array ( [id] => 9934072 [patent_doc_number] => 20150082263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'MERIT-BASED CHARACTERIZATION OF ASSERTIONS IN HARDWARE DESIGN VERIFICATION' [patent_app_type] => utility [patent_app_number] => 14/031949 [patent_app_country] => US [patent_app_date] => 2013-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 13187 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14031949 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/031949
Merit-based characterization of assertions in hardware design verification Sep 18, 2013 Issued
Array ( [id] => 9758993 [patent_doc_number] => 20140289693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SYSTEM AND METHOD FOR IMPROVED NET ROUTING' [patent_app_type] => utility [patent_app_number] => 14/029728 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7688 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14029728 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/029728
SYSTEM AND METHOD FOR IMPROVED NET ROUTING Sep 16, 2013 Abandoned
Array ( [id] => 9386402 [patent_doc_number] => 20140089885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'ELECTRONIC CIRCUIT DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 14/028188 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14028188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/028188
Electronic circuit design method Sep 15, 2013 Issued
Array ( [id] => 9934070 [patent_doc_number] => 20150082262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'DYNAMICALLY GENERATING JOG PATCHES FOR JOG VIOLATIONS' [patent_app_type] => utility [patent_app_number] => 14/027329 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14027329 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/027329
Dynamically generating jog patches for jog violations Sep 15, 2013 Issued
Array ( [id] => 10834850 [patent_doc_number] => 08863044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'Layout assessment method and system' [patent_app_type] => utility [patent_app_number] => 14/020089 [patent_app_country] => US [patent_app_date] => 2013-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10247 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14020089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/020089
Layout assessment method and system Sep 5, 2013 Issued
Array ( [id] => 11214013 [patent_doc_number] => 09443051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Generating root cause candidates for yield analysis' [patent_app_type] => utility [patent_app_number] => 13/973998 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3416 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13973998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/973998
Generating root cause candidates for yield analysis Aug 21, 2013 Issued
Array ( [id] => 9200596 [patent_doc_number] => 20130339911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'STITCH AND TRIM METHODS FOR DOUBLE PATTERNING COMPLIANT STANDARD CELL DESIGN' [patent_app_type] => utility [patent_app_number] => 13/970636 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13970636 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/970636
Stitch and trim methods for double patterning compliant standard cell design Aug 19, 2013 Issued
Array ( [id] => 10834848 [patent_doc_number] => 08863043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'Inspection data generator, inspection data generating method and pattern inspecting method' [patent_app_type] => utility [patent_app_number] => 13/970839 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4118 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13970839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/970839
Inspection data generator, inspection data generating method and pattern inspecting method Aug 19, 2013 Issued
Array ( [id] => 9752374 [patent_doc_number] => 08843864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Statistical corner evaluation for complex on-chip variation model' [patent_app_type] => utility [patent_app_number] => 13/969297 [patent_app_country] => US [patent_app_date] => 2013-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4745 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13969297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/969297
Statistical corner evaluation for complex on-chip variation model Aug 15, 2013 Issued
Array ( [id] => 9886124 [patent_doc_number] => 08972910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-03 [patent_title] => 'Routing method' [patent_app_type] => utility [patent_app_number] => 13/967913 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4842 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/967913
Routing method Aug 14, 2013 Issued
Array ( [id] => 9926465 [patent_doc_number] => 08984452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Long-range lithographic dose correction' [patent_app_type] => utility [patent_app_number] => 13/966013 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966013 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966013
Long-range lithographic dose correction Aug 12, 2013 Issued
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