Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9707526 [patent_doc_number] => 08832622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-09 [patent_title] => 'Coverage scoreboard' [patent_app_type] => utility [patent_app_number] => 13/675555 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3526 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675555
Coverage scoreboard Nov 12, 2012 Issued
Array ( [id] => 9264997 [patent_doc_number] => 20130346926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'Automatic optimal integrated circuit generator from algorithms and specification' [patent_app_type] => utility [patent_app_number] => 13/672822 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672822 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672822
Automatic optimal integrated circuit generator from algorithms and specification Nov 8, 2012 Abandoned
Array ( [id] => 9431147 [patent_doc_number] => 08707234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'Circuit noise extraction using forced input noise waveform' [patent_app_type] => utility [patent_app_number] => 13/672999 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672999 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672999
Circuit noise extraction using forced input noise waveform Nov 8, 2012 Issued
Array ( [id] => 9465573 [patent_doc_number] => 20140130000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'STRUCTURAL RULE ANALYSIS WITH TCL SCRIPTS IN SYNTHESIS OR STA TOOLS AND INTEGRATED CIRCUIT DESIGN TOOLS' [patent_app_type] => utility [patent_app_number] => 13/671070 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671070
Structural rule analysis with TCL scripts in synthesis or STA tools and integrated circuit design tools Nov 6, 2012 Issued
Array ( [id] => 9465574 [patent_doc_number] => 20140130001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'Method of Reducing Parasitic Mismatch' [patent_app_type] => utility [patent_app_number] => 13/670130 [patent_app_country] => US [patent_app_date] => 2012-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670130 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670130
Method of reducing parasitic mismatch Nov 5, 2012 Issued
Array ( [id] => 9451914 [patent_doc_number] => 20140123084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'System and Method for Improving a Lithography Simulation Model' [patent_app_type] => utility [patent_app_number] => 13/666270 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13666270 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/666270
System and Method for Improving a Lithography Simulation Model Oct 31, 2012 Abandoned
Array ( [id] => 9049393 [patent_doc_number] => 08543951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow' [patent_app_type] => utility [patent_app_number] => 13/649909 [patent_app_country] => US [patent_app_date] => 2012-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4583 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649909 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/649909
Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow Oct 10, 2012 Issued
Array ( [id] => 8757176 [patent_doc_number] => 20130091481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'METHOD OF SCHEMATIC DRIVEN LAYOUT CREATION' [patent_app_type] => utility [patent_app_number] => 13/646664 [patent_app_country] => US [patent_app_date] => 2012-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3294 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646664
Method of schematic driven layout creation Oct 5, 2012 Issued
Array ( [id] => 9398691 [patent_doc_number] => 20140096097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'CORE WRAPPING IN THE PRESENCE OF AN EMBEDDED WRAPPED CORE' [patent_app_type] => utility [patent_app_number] => 13/633334 [patent_app_country] => US [patent_app_date] => 2012-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7626 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13633334 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/633334
Core wrapping in the presence of an embedded wrapped core Oct 1, 2012 Issued
Array ( [id] => 9169974 [patent_doc_number] => 08595668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-26 [patent_title] => 'Circuits and methods for efficient clock and data delay configuration for faster timing closure' [patent_app_type] => utility [patent_app_number] => 13/627054 [patent_app_country] => US [patent_app_date] => 2012-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4831 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13627054 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/627054
Circuits and methods for efficient clock and data delay configuration for faster timing closure Sep 25, 2012 Issued
Array ( [id] => 8992070 [patent_doc_number] => 20130219351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'METHOD OF DESIGNING A PHOTO MASK LAYOUT' [patent_app_type] => utility [patent_app_number] => 13/626120 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13626120 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/626120
METHOD OF DESIGNING A PHOTO MASK LAYOUT Sep 24, 2012 Abandoned
Array ( [id] => 9071311 [patent_doc_number] => 20130263067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION' [patent_app_type] => utility [patent_app_number] => 13/626878 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13626878 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/626878
AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION Sep 24, 2012 Abandoned
Array ( [id] => 8824039 [patent_doc_number] => 20130125084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'WIRING-DESIGN SUPPORT DEVICE, RECORDING MEDIUM FOR WIRING-DESIGN SUPPORT PROGRAM, AND METHOD FOR WIRING-DESIGN SUPPORT' [patent_app_type] => utility [patent_app_number] => 13/625300 [patent_app_country] => US [patent_app_date] => 2012-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16909 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13625300 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/625300
Wiring-design support device, recording medium for wiring-design support program, and method for wiring-design support Sep 23, 2012 Issued
Array ( [id] => 9683124 [patent_doc_number] => 20140239887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'BATTERY CHARGER' [patent_app_type] => utility [patent_app_number] => 14/349611 [patent_app_country] => US [patent_app_date] => 2012-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4314 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14349611 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/349611
Battery charger Sep 18, 2012 Issued
Array ( [id] => 10439495 [patent_doc_number] => 20150324507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'PRINTED CIRCUIT BOARD DESIGN VERIFICATION SYSTEM, PRINTED CIRCUIT BOARD DESIGN VERIFICATION METHOD, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/411996 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 21532 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14411996 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/411996
PRINTED CIRCUIT BOARD DESIGN VERIFICATION SYSTEM, PRINTED CIRCUIT BOARD DESIGN VERIFICATION METHOD, AND RECORDING MEDIUM Sep 12, 2012 Abandoned
Array ( [id] => 8899596 [patent_doc_number] => 08479130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-02 [patent_title] => 'Method of designing integrated circuit that accounts for device aging' [patent_app_type] => utility [patent_app_number] => 13/607787 [patent_app_country] => US [patent_app_date] => 2012-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3583 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607787 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/607787
Method of designing integrated circuit that accounts for device aging Sep 8, 2012 Issued
Array ( [id] => 9130357 [patent_doc_number] => 08578314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-05 [patent_title] => 'Circuit design with growable capacitor arrays' [patent_app_type] => utility [patent_app_number] => 13/604814 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8578 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604814
Circuit design with growable capacitor arrays Sep 5, 2012 Issued
Array ( [id] => 9023650 [patent_doc_number] => 08533649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Reducing leakage power in integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 13/597227 [patent_app_country] => US [patent_app_date] => 2012-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7067 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13597227 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/597227
Reducing leakage power in integrated circuit designs Aug 27, 2012 Issued
Array ( [id] => 10895117 [patent_doc_number] => 08918748 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-23 [patent_title] => 'M/A for performing automatic latency optimization on system designs for implementation on programmable hardware' [patent_app_type] => utility [patent_app_number] => 13/593665 [patent_app_country] => US [patent_app_date] => 2012-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13593665 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/593665
M/A for performing automatic latency optimization on system designs for implementation on programmable hardware Aug 23, 2012 Issued
Array ( [id] => 8681402 [patent_doc_number] => 20130049686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'CONTROL CIRCUIT FOR LIMITING A LOAD CURRENT, CHARGING CIRCUIT AND MOTOR VEHICLE' [patent_app_type] => utility [patent_app_number] => 13/592572 [patent_app_country] => US [patent_app_date] => 2012-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13592572 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/592572
Control circuit for limiting a load current, charging circuit and motor vehicle Aug 22, 2012 Issued
Menu