Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9133281 [patent_doc_number] => 20130293995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'NON-SEQUENTIAL MONITORING OF BATTERY CELLS IN BATTERY MONITORING SYSTEMS, AND RELATED COMPONENTS, SYSTEMS, AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/461862 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7556 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461862 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461862
Non-sequential monitoring of battery cells in battery monitoring systems, and related components, systems, and methods May 1, 2012 Issued
Array ( [id] => 10867338 [patent_doc_number] => 08893068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-18 [patent_title] => 'Techniques to generate a more accurate simulation model' [patent_app_type] => utility [patent_app_number] => 13/461143 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461143
Techniques to generate a more accurate simulation model Apr 30, 2012 Issued
Array ( [id] => 8507039 [patent_doc_number] => 20120306447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'APPARATUS FOR STABILIZING VOLTAGE OF ENERGY STORAGE' [patent_app_type] => utility [patent_app_number] => 13/461481 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3380 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461481
APPARATUS FOR STABILIZING VOLTAGE OF ENERGY STORAGE Apr 30, 2012 Abandoned
Array ( [id] => 9971899 [patent_doc_number] => 09018915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Battery protection circuit and method of controlling the same' [patent_app_type] => utility [patent_app_number] => 13/461320 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4089 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461320
Battery protection circuit and method of controlling the same Apr 30, 2012 Issued
Array ( [id] => 8959162 [patent_doc_number] => 08504956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-06 [patent_title] => 'Calculation of integrated circuit timing delay using frequency domain' [patent_app_type] => utility [patent_app_number] => 13/460814 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6537 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/460814
Calculation of integrated circuit timing delay using frequency domain Apr 29, 2012 Issued
Array ( [id] => 8878905 [patent_doc_number] => 08473890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Timing error sampling generator and a method of timing testing' [patent_app_type] => utility [patent_app_number] => 13/460605 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4749 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460605 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/460605
Timing error sampling generator and a method of timing testing Apr 29, 2012 Issued
Array ( [id] => 8810431 [patent_doc_number] => 08448098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Fracturing continuous photolithography masks' [patent_app_type] => utility [patent_app_number] => 13/453262 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13453262 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/453262
Fracturing continuous photolithography masks Apr 22, 2012 Issued
Array ( [id] => 10890740 [patent_doc_number] => 08914754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Database-driven cell-to-cell reticle inspection' [patent_app_type] => utility [patent_app_number] => 13/809825 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2264 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13809825 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/809825
Database-driven cell-to-cell reticle inspection Apr 22, 2012 Issued
Array ( [id] => 8627061 [patent_doc_number] => 08359565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Method and apparatus for generating test patterns for use in at-speed testing' [patent_app_type] => utility [patent_app_number] => 13/439188 [patent_app_country] => US [patent_app_date] => 2012-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3873 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439188 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/439188
Method and apparatus for generating test patterns for use in at-speed testing Apr 3, 2012 Issued
Array ( [id] => 9044352 [patent_doc_number] => 20130246990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'SYSTEM AND METHOD FOR MODELING THROUGH SILICON VIA' [patent_app_type] => utility [patent_app_number] => 13/419959 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419959 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419959
System and method for modeling through silicon via Mar 13, 2012 Issued
Array ( [id] => 10067214 [patent_doc_number] => 09106077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Power control apparatus and power control method' [patent_app_type] => utility [patent_app_number] => 13/816582 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 12514 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13816582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/816582
Power control apparatus and power control method Mar 13, 2012 Issued
Array ( [id] => 9077619 [patent_doc_number] => 08555211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Mask making with error recognition' [patent_app_type] => utility [patent_app_number] => 13/416897 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 3750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416897 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416897
Mask making with error recognition Mar 8, 2012 Issued
Array ( [id] => 9029798 [patent_doc_number] => 08539396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Stitch and trim methods for double patterning compliant standard cell design' [patent_app_type] => utility [patent_app_number] => 13/415997 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 6271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13415997 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/415997
Stitch and trim methods for double patterning compliant standard cell design Mar 8, 2012 Issued
Array ( [id] => 9630139 [patent_doc_number] => 08799833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'System and methods for converting planar design to FinFET design' [patent_app_type] => utility [patent_app_number] => 13/416907 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 13903 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416907 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416907
System and methods for converting planar design to FinFET design Mar 8, 2012 Issued
Array ( [id] => 9029798 [patent_doc_number] => 08539396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Stitch and trim methods for double patterning compliant standard cell design' [patent_app_type] => utility [patent_app_number] => 13/415997 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 6271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13415997 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/415997
Stitch and trim methods for double patterning compliant standard cell design Mar 8, 2012 Issued
Array ( [id] => 8267596 [patent_doc_number] => 20120167022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES' [patent_app_type] => utility [patent_app_number] => 13/410386 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13410386 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/410386
METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES Mar 1, 2012 Abandoned
Array ( [id] => 8851364 [patent_doc_number] => 20130141039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'ELECTRICAL POWER RECEIVING APPARATUS AND ELECTRICAL POWER RECEIVING METHOD' [patent_app_type] => utility [patent_app_number] => 13/816783 [patent_app_country] => US [patent_app_date] => 2012-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6958 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13816783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/816783
Electrical power receiving apparatus and electrical power receiving method Feb 22, 2012 Issued
Array ( [id] => 8686887 [patent_doc_number] => 20130055171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'Method, Program Product and Apparatus for Performing Double Exposure Lithography' [patent_app_type] => utility [patent_app_number] => 13/401820 [patent_app_country] => US [patent_app_date] => 2012-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13401820 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/401820
Method, program product and apparatus for performing double exposure lithography Feb 20, 2012 Issued
Array ( [id] => 11201624 [patent_doc_number] => 09431847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Communication device, communication method, battery device, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 13/984073 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5963 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13984073 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/984073
Communication device, communication method, battery device, and electronic apparatus Feb 13, 2012 Issued
Array ( [id] => 8752243 [patent_doc_number] => 08418087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance' [patent_app_type] => utility [patent_app_number] => 13/371537 [patent_app_country] => US [patent_app_date] => 2012-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4993 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13371537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/371537
Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance Feb 12, 2012 Issued
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