Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8181062 [patent_doc_number] => 20120112827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/231693 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112827.pdf [firstpage_image] =>[orig_patent_app_number] => 13231693 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/231693
APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT Sep 12, 2011 Abandoned
Array ( [id] => 8929921 [patent_doc_number] => 20130185681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'CORRECTION FOR FLARE EFFECTS IN LITHOGRAPHY SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/823685 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 13429 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13823685 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/823685
Correction for flare effects in lithography system Aug 31, 2011 Issued
Array ( [id] => 8214298 [patent_doc_number] => 20120131531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Reducing Leakage Power in Integrated Circuit Designs' [patent_app_type] => utility [patent_app_number] => 13/220603 [patent_app_country] => US [patent_app_date] => 2011-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7019 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131531.pdf [firstpage_image] =>[orig_patent_app_number] => 13220603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/220603
Reducing leakage power in integrated circuit designs Aug 28, 2011 Issued
Array ( [id] => 8799631 [patent_doc_number] => 08438520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Early decoupling capacitor optimization method for hierarchical circuit design' [patent_app_type] => utility [patent_app_number] => 13/219813 [patent_app_country] => US [patent_app_date] => 2011-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11028 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219813 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219813
Early decoupling capacitor optimization method for hierarchical circuit design Aug 28, 2011 Issued
Array ( [id] => 8728498 [patent_doc_number] => 08407640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Sensitivity-based complex statistical modeling for random on-chip variation' [patent_app_type] => utility [patent_app_number] => 13/199222 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4735 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13199222 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/199222
Sensitivity-based complex statistical modeling for random on-chip variation Aug 22, 2011 Issued
Array ( [id] => 8497948 [patent_doc_number] => 20120297356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'COMPUTING DEVICE AND METHOD FOR INSPECTING LAYOUT OF PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 13/213072 [patent_app_country] => US [patent_app_date] => 2011-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1778 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13213072 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/213072
Computing device and method for inspecting layout of printed circuit board Aug 17, 2011 Issued
Array ( [id] => 7780738 [patent_doc_number] => 20120042294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 13/209702 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3314 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042294.pdf [firstpage_image] =>[orig_patent_app_number] => 13209702 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209702
Apparatus and method thereof for hybrid timing exception verification of an integrated circuit design Aug 14, 2011 Issued
Array ( [id] => 8878898 [patent_doc_number] => 08473883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Abstraction for arrays in integrated circuit models' [patent_app_type] => utility [patent_app_number] => 13/197061 [patent_app_country] => US [patent_app_date] => 2011-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 11741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13197061 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/197061
Abstraction for arrays in integrated circuit models Aug 2, 2011 Issued
Array ( [id] => 8574914 [patent_doc_number] => 08341577 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Parallel circuit simulation with partitions' [patent_app_type] => utility [patent_app_number] => 13/191603 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7691 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/191603
Parallel circuit simulation with partitions Jul 26, 2011 Issued
Array ( [id] => 8639719 [patent_doc_number] => 20130031522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'HOTSPOT DETECTION BASED ON MACHINE LEARNING' [patent_app_type] => utility [patent_app_number] => 13/191433 [patent_app_country] => US [patent_app_date] => 2011-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191433 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/191433
Hotspot detection based on machine learning Jul 25, 2011 Issued
Array ( [id] => 8639721 [patent_doc_number] => 20130031523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/190083 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7574 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13190083 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/190083
Systems and methods for correlated parameters in statistical static timing analysis Jul 24, 2011 Issued
Array ( [id] => 8861636 [patent_doc_number] => 08464191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'System and method for identifying circuit components of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/187912 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5165 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13187912 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187912
System and method for identifying circuit components of an integrated circuit Jul 20, 2011 Issued
Array ( [id] => 8480947 [patent_doc_number] => 20120280354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES' [patent_app_type] => utility [patent_app_number] => 13/101665 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13101665 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/101665
METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES May 4, 2011 Abandoned
Array ( [id] => 7493383 [patent_doc_number] => 20110239175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium' [patent_app_type] => utility [patent_app_number] => 13/064805 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9375 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239175.pdf [firstpage_image] =>[orig_patent_app_number] => 13064805 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064805
Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium Apr 17, 2011 Issued
Array ( [id] => 8455177 [patent_doc_number] => 20120266123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIATION IN ELECTRONIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/084582 [patent_app_country] => US [patent_app_date] => 2011-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13084582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/084582
COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIATION IN ELECTRONIC CIRCUITS Apr 11, 2011 Abandoned
Array ( [id] => 8432943 [patent_doc_number] => 20120254818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING FULL-CHIP OPTIMIZATION WITH REDUCED PHYSICAL DESIGN DATA' [patent_app_type] => utility [patent_app_number] => 13/077933 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15120 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13077933 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/077933
Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data Mar 30, 2011 Issued
Array ( [id] => 8060143 [patent_doc_number] => 20110246955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METHOD, PROGRAM, AND APPARATUS FOR AIDING WIRING DESIGN' [patent_app_type] => utility [patent_app_number] => 13/075632 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 104 [patent_figures_cnt] => 104 [patent_no_of_words] => 62284 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246955.pdf [firstpage_image] =>[orig_patent_app_number] => 13075632 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075632
Method, program, and apparatus for aiding wiring design Mar 29, 2011 Issued
Array ( [id] => 7694782 [patent_doc_number] => 20110231808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'PACKAGING DESIGN AIDING DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/048593 [patent_app_country] => US [patent_app_date] => 2011-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7374 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20110231808.pdf [firstpage_image] =>[orig_patent_app_number] => 13048593 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/048593
Packaging design aiding device and method Mar 14, 2011 Issued
Array ( [id] => 8805039 [patent_doc_number] => 08443324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Routing and timing using layer ranges' [patent_app_type] => utility [patent_app_number] => 13/047492 [patent_app_country] => US [patent_app_date] => 2011-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6929 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13047492 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/047492
Routing and timing using layer ranges Mar 13, 2011 Issued
Array ( [id] => 8693325 [patent_doc_number] => 08392861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Method of semiconductor integrated circuit device using library for estimating timing/area to place cells' [patent_app_type] => utility [patent_app_number] => 13/046752 [patent_app_country] => US [patent_app_date] => 2011-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 6674 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13046752 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/046752
Method of semiconductor integrated circuit device using library for estimating timing/area to place cells Mar 12, 2011 Issued
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