
Anne Marie Sabrina Wehbe
Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )
| Most Active Art Unit | 1633 |
| Art Unit(s) | 1632, 1634, 1633 |
| Total Applications | 1343 |
| Issued Applications | 603 |
| Pending Applications | 241 |
| Abandoned Applications | 542 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7493389
[patent_doc_number] => 20110239181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'WIRING DESIGN METHOD AND COMPUTER-READABLE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 13/045422
[patent_app_country] => US
[patent_app_date] => 2011-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9745
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20110239181.pdf
[firstpage_image] =>[orig_patent_app_number] => 13045422
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/045422 | WIRING DESIGN METHOD AND COMPUTER-READABLE MEDIUM | Mar 9, 2011 | Abandoned |
Array
(
[id] => 6094366
[patent_doc_number] => 20110219342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-08
[patent_title] => 'Design Rule Optimization in Lithographic Imaging Based on Correlation of Functions Representing Mask and Predefined Optical Conditions'
[patent_app_type] => utility
[patent_app_number] => 13/042303
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10493
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0219/20110219342.pdf
[firstpage_image] =>[orig_patent_app_number] => 13042303
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/042303 | Rule optimization in lithographic imaging based on correlation of functions representing mask and predefined optical conditions | Mar 6, 2011 | Issued |
Array
(
[id] => 8574908
[patent_doc_number] => 08341571
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-12-25
[patent_title] => 'Pattern signature'
[patent_app_type] => utility
[patent_app_number] => 13/042414
[patent_app_country] => US
[patent_app_date] => 2011-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3666
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13042414
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/042414 | Pattern signature | Mar 6, 2011 | Issued |
Array
(
[id] => 8899603
[patent_doc_number] => 08479137
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-02
[patent_title] => 'Apparatus and method for preventing congestive placement'
[patent_app_type] => utility
[patent_app_number] => 13/040512
[patent_app_country] => US
[patent_app_date] => 2011-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 3986
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13040512
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/040512 | Apparatus and method for preventing congestive placement | Mar 3, 2011 | Issued |
Array
(
[id] => 8372596
[patent_doc_number] => 20120221985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'METHOD AND SYSTEM FOR DESIGN OF A SURFACE TO BE MANUFACTURED USING CHARGED PARTICLE BEAM LITHOGRAPHY'
[patent_app_type] => utility
[patent_app_number] => 13/037263
[patent_app_country] => US
[patent_app_date] => 2011-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10016
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037263
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/037263 | METHOD AND SYSTEM FOR DESIGN OF A SURFACE TO BE MANUFACTURED USING CHARGED PARTICLE BEAM LITHOGRAPHY | Feb 27, 2011 | Abandoned |
Array
(
[id] => 8360992
[patent_doc_number] => 20120216155
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-23
[patent_title] => 'CHECKING METHOD FOR MASK DESIGN OF INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/033582
[patent_app_country] => US
[patent_app_date] => 2011-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1785
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13033582
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/033582 | CHECKING METHOD FOR MASK DESIGN OF INTEGRATED CIRCUIT | Feb 22, 2011 | Abandoned |
Array
(
[id] => 8946078
[patent_doc_number] => 08499265
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-30
[patent_title] => 'Circuit for detecting and preventing setup fails and the method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/026653
[patent_app_country] => US
[patent_app_date] => 2011-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2608
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13026653
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/026653 | Circuit for detecting and preventing setup fails and the method thereof | Feb 13, 2011 | Issued |
Array
(
[id] => 8333643
[patent_doc_number] => 20120200347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-09
[patent_title] => 'SKEWED PLACEMENT GRID FOR VERY LARGE SCALE INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 13/022913
[patent_app_country] => US
[patent_app_date] => 2011-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4704
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13022913
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/022913 | Skewed placement grid for very large scale integrated circuits | Feb 7, 2011 | Issued |
Array
(
[id] => 6040783
[patent_doc_number] => 20110093832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-21
[patent_title] => 'PRINTED CIRCUIT BOARD DESIGN SUPPORT APPARATUS, METHOD, AND PROGRAM MEDIUM THEREFOR'
[patent_app_type] => utility
[patent_app_number] => 12/978767
[patent_app_country] => US
[patent_app_date] => 2010-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 9458
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20110093832.pdf
[firstpage_image] =>[orig_patent_app_number] => 12978767
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/978767 | Printed circuit board design support apparatus, method, and recording medium storing program therefor | Dec 26, 2010 | Issued |
Array
(
[id] => 9392538
[patent_doc_number] => 08689163
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-01
[patent_title] => 'Semiconductor apparatus capable of error revision using pin extension technique and design method therefor'
[patent_app_type] => utility
[patent_app_number] => 12/928021
[patent_app_country] => US
[patent_app_date] => 2010-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 4440
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12928021
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/928021 | Semiconductor apparatus capable of error revision using pin extension technique and design method therefor | Nov 30, 2010 | Issued |
Array
(
[id] => 8201993
[patent_doc_number] => 20120124543
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-17
[patent_title] => 'FLIP-FLOP LIBRARY DEVELOPMENT FOR HIGH FREQUENCY DESIGNS BUILT IN AN ASIC FLOW'
[patent_app_type] => utility
[patent_app_number] => 12/948481
[patent_app_country] => US
[patent_app_date] => 2010-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9159
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20120124543.pdf
[firstpage_image] =>[orig_patent_app_number] => 12948481
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/948481 | Flip-flop library development for high frequency designs built in an ASIC flow | Nov 16, 2010 | Issued |
Array
(
[id] => 7493386
[patent_doc_number] => 20110239178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-29
[patent_title] => 'LAYOUT DESIGN APPARATUS, LAYOUT DESIGN METHOD, AND COMPUTER READABLE MEDIUM HAVING A LAYOUT DESIGN PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 12/947331
[patent_app_country] => US
[patent_app_date] => 2010-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 16656
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0239/20110239178.pdf
[firstpage_image] =>[orig_patent_app_number] => 12947331
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/947331 | LAYOUT DESIGN APPARATUS, LAYOUT DESIGN METHOD, AND COMPUTER READABLE MEDIUM HAVING A LAYOUT DESIGN PROGRAM | Nov 15, 2010 | Abandoned |
Array
(
[id] => 8752263
[patent_doc_number] => 08418107
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-09
[patent_title] => 'Performing statistical timing analysis with non-separable statistical and deterministic variations'
[patent_app_type] => utility
[patent_app_number] => 12/943541
[patent_app_country] => US
[patent_app_date] => 2010-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5276
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12943541
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/943541 | Performing statistical timing analysis with non-separable statistical and deterministic variations | Nov 9, 2010 | Issued |
Array
(
[id] => 9156926
[patent_doc_number] => 08589840
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-19
[patent_title] => 'Semiconductor chip design verification device'
[patent_app_type] => utility
[patent_app_number] => 12/914801
[patent_app_country] => US
[patent_app_date] => 2010-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 24
[patent_no_of_words] => 13235
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12914801
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/914801 | Semiconductor chip design verification device | Oct 27, 2010 | Issued |
Array
(
[id] => 8985302
[patent_doc_number] => 08516432
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-20
[patent_title] => 'Method and device for reconstructing scan chain based on bidirectional preference selection in physical design'
[patent_app_type] => utility
[patent_app_number] => 13/503613
[patent_app_country] => US
[patent_app_date] => 2010-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 7486
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13503613
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/503613 | Method and device for reconstructing scan chain based on bidirectional preference selection in physical design | Oct 26, 2010 | Issued |
Array
(
[id] => 5981260
[patent_doc_number] => 20110095802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-28
[patent_title] => 'Semiconductor device and designing method of the same'
[patent_app_type] => utility
[patent_app_number] => 12/926001
[patent_app_country] => US
[patent_app_date] => 2010-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8901
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20110095802.pdf
[firstpage_image] =>[orig_patent_app_number] => 12926001
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/926001 | Semiconductor device and designing method of the same | Oct 19, 2010 | Issued |
Array
(
[id] => 8574909
[patent_doc_number] => 08341573
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-25
[patent_title] => 'Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow'
[patent_app_type] => utility
[patent_app_number] => 12/905301
[patent_app_country] => US
[patent_app_date] => 2010-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4746
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12905301
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/905301 | Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow | Oct 14, 2010 | Issued |
Array
(
[id] => 8096609
[patent_doc_number] => 20120083913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/897021
[patent_app_country] => US
[patent_app_date] => 2010-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4141
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20120083913.pdf
[firstpage_image] =>[orig_patent_app_number] => 12897021
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/897021 | Semiconductor layer forming method and structure | Oct 3, 2010 | Issued |
Array
(
[id] => 6125948
[patent_doc_number] => 20110078646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-31
[patent_title] => 'SUPPORT APPARATUS AND DESIGN SUPPORT METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/892481
[patent_app_country] => US
[patent_app_date] => 2010-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 6651
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0078/20110078646.pdf
[firstpage_image] =>[orig_patent_app_number] => 12892481
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/892481 | Apparatus and method for design support using layout positions of first and second terminals | Sep 27, 2010 | Issued |
Array
(
[id] => 8208384
[patent_doc_number] => 08191035
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-05-29
[patent_title] => 'Tool with graphical interconnect matrix'
[patent_app_type] => utility
[patent_app_number] => 12/860629
[patent_app_country] => US
[patent_app_date] => 2010-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 8853
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 362
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/191/08191035.pdf
[firstpage_image] =>[orig_patent_app_number] => 12860629
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/860629 | Tool with graphical interconnect matrix | Aug 19, 2010 | Issued |