Anne Marie Sabrina Wehbe

Array ( [id] => 8389145 [patent_doc_number] => 08266556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Fracturing continuous photolithography masks' [patent_app_type] => utility [patent_app_number] => 12/849171 [patent_app_country] => US [patent_app_date] => 2010-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9006 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12849171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6032164 [patent_doc_number] => 20110055787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Interface Configuration System and Method' [patent_app_type] => utility [patent_app_number] => 12/849781 [patent_app_country] => US [patent_app_date] => 2010-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3201 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055787.pdf [firstpage_image] =>[orig_patent_app_number] => 12849781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6032138 [patent_doc_number] => 20110055776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHOD OF DESIGNING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/837061 [patent_app_country] => US [patent_app_date] => 2010-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055776.pdf [firstpage_image] =>[orig_patent_app_number] => 12837061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6171981 [patent_doc_number] => 20110197172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'Design verification apparatus and design verification program' [patent_app_type] => utility [patent_app_number] => 12/805141 [patent_app_country] => US [patent_app_date] => 2010-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 21158 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20110197172.pdf [firstpage_image] =>[orig_patent_app_number] => 12805141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8319808 [patent_doc_number] => 08234603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Method for fast estimation of lithographic binding patterns in an integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 12/835891 [patent_app_country] => US [patent_app_date] => 2010-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 7496 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12835891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8645785 [patent_doc_number] => 08370784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Automatic optimal integrated circuit generator from algorithms and specification' [patent_app_type] => utility [patent_app_number] => 12/835621 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6152 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12835621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7768476 [patent_doc_number] => 08117586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Printed circuit board layout system and method thereof' [patent_app_type] => utility [patent_app_number] => 12/835701 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1764 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117586.pdf [firstpage_image] =>[orig_patent_app_number] => 12835701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8860551 [patent_doc_number] => 08463097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Planar lightwave circuit, design method for wave propagation circuit, and computer program' [patent_app_type] => utility [patent_app_number] => 12/834561 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 54 [patent_no_of_words] => 25139 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12834561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9990405 [patent_doc_number] => 09035613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Parallel circuit of accumulator lines' [patent_app_type] => utility [patent_app_number] => 13/391867 [patent_app_country] => US [patent_app_date] => 2010-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2160 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13391867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10159084 [patent_doc_number] => 09190869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Circuit for operating an auxiliary unit for starting internal combustion engines' [patent_app_type] => utility [patent_app_number] => 13/390659 [patent_app_country] => US [patent_app_date] => 2010-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2586 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13390659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8655581 [patent_doc_number] => 08375349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-12 [patent_title] => 'Method for constant power density scaling' [patent_app_type] => utility [patent_app_number] => 12/828591 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4330 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12828591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9555835 [patent_doc_number] => 08762908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-24 [patent_title] => 'Static timing analysis with design-specific on chip variation de-rating factors' [patent_app_type] => utility [patent_app_number] => 12/824194 [patent_app_country] => US [patent_app_date] => 2010-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8708 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8561939 [patent_doc_number] => 08336010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-18 [patent_title] => 'Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/824191 [patent_app_country] => US [patent_app_date] => 2010-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6466001 [patent_doc_number] => 20100146468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'SYSTEM AND METHOD FOR DESIGNING MULTIPLE CLOCK DOMAIN CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/706470 [patent_app_country] => US [patent_app_date] => 2010-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7573 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146468.pdf [firstpage_image] =>[orig_patent_app_number] => 12706470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6612488 [patent_doc_number] => 20100131909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'FAST LITHOGRAPHY COMPLIANCE CHECK FOR PLACE AND ROUTE OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/696427 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20100131909.pdf [firstpage_image] =>[orig_patent_app_number] => 12696427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5960950 [patent_doc_number] => 20110185337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'METHODOLOGY FOR STORING AND UPDATING ON-CHIP REVISION LEVEL' [patent_app_type] => utility [patent_app_number] => 12/691973 [patent_app_country] => US [patent_app_date] => 2010-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185337.pdf [firstpage_image] =>[orig_patent_app_number] => 12691973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5960948 [patent_doc_number] => 20110185335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'DETERMINING AN ORDER FOR VISITING CIRCUIT BLOCKS IN A CIRCUIT DESIGN FOR FIXING DESIGN REQUIREMENT VIOLATIONS' [patent_app_type] => utility [patent_app_number] => 12/692073 [patent_app_country] => US [patent_app_date] => 2010-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185335.pdf [firstpage_image] =>[orig_patent_app_number] => 12692073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7780226 [patent_doc_number] => 08122391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Method, program product and apparatus for performing double exposure lithography' [patent_app_type] => utility [patent_app_number] => 12/691552 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 7143 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122391.pdf [firstpage_image] =>[orig_patent_app_number] => 12691552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6410462 [patent_doc_number] => 20100180241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'METHOD OF DESIGNING SEMICONDUCTOR DEVICE AND DESIGN PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/688101 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13371 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20100180241.pdf [firstpage_image] =>[orig_patent_app_number] => 12688101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8120433 [patent_doc_number] => 08161443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'System for analyzing sensitivity of parasitic capacitance to variation of semiconductor design parameters' [patent_app_type] => utility [patent_app_number] => 12/688103 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13248 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161443.pdf [firstpage_image] =>[orig_patent_app_number] => 12688103 [rel_patent_id] =>[rel_patent_doc_number] =>)