Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7746697 [patent_doc_number] => 08108821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Reduction of logic and delay through latch polarity inversion' [patent_app_type] => utility [patent_app_number] => 12/685803 [patent_app_country] => US [patent_app_date] => 2010-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5346 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108821.pdf [firstpage_image] =>[orig_patent_app_number] => 12685803 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685803
Reduction of logic and delay through latch polarity inversion Jan 11, 2010 Issued
Array ( [id] => 8971855 [patent_doc_number] => 08510685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-13 [patent_title] => 'Methods, systems, and articles of manufacture for creating a hierarchical output for an operation in an electronic design' [patent_app_type] => utility [patent_app_number] => 12/649643 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10444 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12649643 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649643
Methods, systems, and articles of manufacture for creating a hierarchical output for an operation in an electronic design Dec 29, 2009 Issued
Array ( [id] => 7582486 [patent_doc_number] => 20110296369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'OPERATION ANALYZING METHOD, OPERATION ANALYZING APPARATUS, OPERATION ANALYZING PROGRAM, AND OPERATION ANALYZING SYSTEM FOR SEMICONDUCTOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/062263 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7717 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296369.pdf [firstpage_image] =>[orig_patent_app_number] => 13062263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/062263
Method, apparatus, and system for analyzing operation of semiconductor integrated circuits Oct 26, 2009 Issued
Array ( [id] => 6125952 [patent_doc_number] => 20110078649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'WAFER LAYOUT ASSISTING METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/571212 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3932 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20110078649.pdf [firstpage_image] =>[orig_patent_app_number] => 12571212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/571212
WAFER LAYOUT ASSISTING METHOD AND SYSTEM Sep 29, 2009 Abandoned
Array ( [id] => 6125951 [patent_doc_number] => 20110078648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'MODULAR ROUTING FABRIC USING SWITCHING NETWORKS' [patent_app_type] => utility [patent_app_number] => 12/568042 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7093 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20110078648.pdf [firstpage_image] =>[orig_patent_app_number] => 12568042 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568042
Modular routing fabric using switching networks Sep 27, 2009 Issued
Array ( [id] => 5982187 [patent_doc_number] => 20110072404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'Parallel Timing Analysis For Place-And-Route Operations' [patent_app_type] => utility [patent_app_number] => 12/566652 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7498 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20110072404.pdf [firstpage_image] =>[orig_patent_app_number] => 12566652 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/566652
Parallel Timing Analysis For Place-And-Route Operations Sep 23, 2009 Abandoned
Array ( [id] => 6480763 [patent_doc_number] => 20100192112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'DIAGNOSTIC APPARATUS FOR SEMICONDUCTOR DEVICE, DIAGNOSTIC METHOD FOR SEMICONDUCTOR DEVICE, AND MEDIUM STORING DIAGNOSTIC PROGRAM FOR SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/563512 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20100192112.pdf [firstpage_image] =>[orig_patent_app_number] => 12563512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563512
DIAGNOSTIC APPARATUS FOR SEMICONDUCTOR DEVICE, DIAGNOSTIC METHOD FOR SEMICONDUCTOR DEVICE, AND MEDIUM STORING DIAGNOSTIC PROGRAM FOR SEMICONDUCTOR DEVICE Sep 20, 2009 Abandoned
Array ( [id] => 8319809 [patent_doc_number] => 08234607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Token enhanced asynchronous conversion of synchonous circuits' [patent_app_type] => utility [patent_app_number] => 12/559612 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3717 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12559612 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559612
Token enhanced asynchronous conversion of synchonous circuits Sep 14, 2009 Issued
Array ( [id] => 6241429 [patent_doc_number] => 20100269080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'COMPUTER-AIDED DESIGN SYSTEM AND METHOD FOR SIMULATING PCB SPECIFICATIONS' [patent_app_type] => utility [patent_app_number] => 12/558682 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2269 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269080.pdf [firstpage_image] =>[orig_patent_app_number] => 12558682 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558682
COMPUTER-AIDED DESIGN SYSTEM AND METHOD FOR SIMULATING PCB SPECIFICATIONS Sep 13, 2009 Abandoned
Array ( [id] => 6204203 [patent_doc_number] => 20110066989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'METHOD AND SYSTEM TO AT LEAST PARTIALLY ISOLATE NETS' [patent_app_type] => utility [patent_app_number] => 12/557872 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066989.pdf [firstpage_image] =>[orig_patent_app_number] => 12557872 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557872
Method and system to at least partially isolate nets Sep 10, 2009 Issued
Array ( [id] => 8775601 [patent_doc_number] => 08429578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Method of verifying logic circuit including decoders and apparatus for the same' [patent_app_type] => utility [patent_app_number] => 12/547462 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9839 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12547462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/547462
Method of verifying logic circuit including decoders and apparatus for the same Aug 24, 2009 Issued
Array ( [id] => 8645788 [patent_doc_number] => 08370787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Testing security of mapping functions' [patent_app_type] => utility [patent_app_number] => 12/547382 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8956 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12547382 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/547382
Testing security of mapping functions Aug 24, 2009 Issued
Array ( [id] => 8627059 [patent_doc_number] => 08359563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Moment-based characterization waveform for static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/542042 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3229 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12542042 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/542042
Moment-based characterization waveform for static timing analysis Aug 16, 2009 Issued
Array ( [id] => 6292954 [patent_doc_number] => 20100159617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'SEMICONDUCTOR-DEVICE MANUFACTURING METHOD AND EXPOSURE METHOD' [patent_app_type] => utility [patent_app_number] => 12/533592 [patent_app_country] => US [patent_app_date] => 2009-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20100159617.pdf [firstpage_image] =>[orig_patent_app_number] => 12533592 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/533592
Semiconductor-device manufacturing method Jul 30, 2009 Issued
Array ( [id] => 10085485 [patent_doc_number] => 09122832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Methods for controlling microloading variation in semiconductor wafer layout and fabrication' [patent_app_type] => utility [patent_app_number] => 12/512932 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 7672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12512932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512932
Methods for controlling microloading variation in semiconductor wafer layout and fabrication Jul 29, 2009 Issued
Array ( [id] => 7982871 [patent_doc_number] => 08074194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Method and apparatus for distinguishing combinational designs' [patent_app_type] => utility [patent_app_number] => 12/506897 [patent_app_country] => US [patent_app_date] => 2009-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 53 [patent_no_of_words] => 14226 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/074/08074194.pdf [firstpage_image] =>[orig_patent_app_number] => 12506897 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/506897
Method and apparatus for distinguishing combinational designs Jul 20, 2009 Issued
Array ( [id] => 8645777 [patent_doc_number] => 08370777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Method of generating a leadframe IC package model, a leadframe modeler and an IC design system' [patent_app_type] => utility [patent_app_number] => 12/485238 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3448 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12485238 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/485238
Method of generating a leadframe IC package model, a leadframe modeler and an IC design system Jun 15, 2009 Issued
Array ( [id] => 6621587 [patent_doc_number] => 20100064266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'VERIFICATION SUPPORT APPARATUS, VERIFICATION SUPPORT METHOD, AND COMPUTER PRODUCT' [patent_app_type] => utility [patent_app_number] => 12/484762 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7900 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064266.pdf [firstpage_image] =>[orig_patent_app_number] => 12484762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484762
Hardware logic verification support apparatus, verification support method and computer product Jun 14, 2009 Issued
Array ( [id] => 5399908 [patent_doc_number] => 20090319971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'METHOD OF VERIFYING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/484431 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2885 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319971.pdf [firstpage_image] =>[orig_patent_app_number] => 12484431 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484431
METHOD OF VERIFYING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Jun 14, 2009 Abandoned
Array ( [id] => 8033893 [patent_doc_number] => 08146040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-27 [patent_title] => 'Method of evaluating an architecture for an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/482687 [patent_app_country] => US [patent_app_date] => 2009-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8485 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146040.pdf [firstpage_image] =>[orig_patent_app_number] => 12482687 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/482687
Method of evaluating an architecture for an integrated circuit device Jun 10, 2009 Issued
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