Anne Marie Sabrina Wehbe

Array ( [id] => 6313154 [patent_doc_number] => 20100070937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'CIRCUIT VERIFICATION APPARATUS, CIRCUIT VERIFICATION METHOD, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/482569 [patent_app_country] => US [patent_app_date] => 2009-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070937.pdf [firstpage_image] =>[orig_patent_app_number] => 12482569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8297457 [patent_doc_number] => 08225258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Statistical integrated circuit package modeling for analysis at the early design age' [patent_app_type] => utility [patent_app_number] => 12/482825 [patent_app_country] => US [patent_app_date] => 2009-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4125 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12482825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5370088 [patent_doc_number] => 20090307647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'LAYOUT DESIGN METHOD AND COMPUTER-READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/482348 [patent_app_country] => US [patent_app_date] => 2009-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307647.pdf [firstpage_image] =>[orig_patent_app_number] => 12482348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9348271 [patent_doc_number] => 08667434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-04 [patent_title] => 'System, method, and computer program product for altering a hardware description based on an instruction file' [patent_app_type] => utility [patent_app_number] => 12/478658 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5364 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12478658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5303553 [patent_doc_number] => 20090298205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Pattern verifying method, pattern verifying device, program, and manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/457105 [patent_app_country] => US [patent_app_date] => 2009-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6605 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20090298205.pdf [firstpage_image] =>[orig_patent_app_number] => 12457105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7530119 [patent_doc_number] => 08046725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Method of incremental statistical static timing analysis based on timing yield' [patent_app_type] => utility [patent_app_number] => 12/475545 [patent_app_country] => US [patent_app_date] => 2009-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3559 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046725.pdf [firstpage_image] =>[orig_patent_app_number] => 12475545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9652351 [patent_doc_number] => 08806387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Model-based process simulation systems and methods' [patent_app_type] => utility [patent_app_number] => 12/475095 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9832 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12475095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8985278 [patent_doc_number] => 08516408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Optimization of circuits having repeatable circuit instances' [patent_app_type] => utility [patent_app_number] => 12/471968 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7406 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12471968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4616658 [patent_doc_number] => 07992111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-02 [patent_title] => 'Conversion of a high-level graphical circuit design block to a high-level language program' [patent_app_type] => utility [patent_app_number] => 12/467678 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5897 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/992/07992111.pdf [firstpage_image] =>[orig_patent_app_number] => 12467678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6534250 [patent_doc_number] => 20100287432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING' [patent_app_type] => utility [patent_app_number] => 12/464025 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3837 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287432.pdf [firstpage_image] =>[orig_patent_app_number] => 12464025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6464946 [patent_doc_number] => 20100281449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'Method For Forming Arbitrary Lithographic Wavefronts Using Standard Mask Technology' [patent_app_type] => utility [patent_app_number] => 12/431865 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 18166 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281449.pdf [firstpage_image] =>[orig_patent_app_number] => 12431865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6241427 [patent_doc_number] => 20100269079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Analyzing Multiple Induced Systematic and Statistical Layout Dependent Effects On Circuit Performance' [patent_app_type] => utility [patent_app_number] => 12/426475 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269079.pdf [firstpage_image] =>[orig_patent_app_number] => 12426475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6241417 [patent_doc_number] => 20100269073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Proprietary circuit layout identification' [patent_app_type] => utility [patent_app_number] => 12/385765 [patent_app_country] => US [patent_app_date] => 2009-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5946 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269073.pdf [firstpage_image] =>[orig_patent_app_number] => 12385765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6241422 [patent_doc_number] => 20100269077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Trace Containment Detection of Combinational Designs via Constraint-Based Uncorrelated Equivalence Checking' [patent_app_type] => utility [patent_app_number] => 12/425095 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7338 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269077.pdf [firstpage_image] =>[orig_patent_app_number] => 12425095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6587655 [patent_doc_number] => 20100235795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'EXECUTION MONITOR FOR ELECTRONIC DESIGN AUTOMATION' [patent_app_type] => utility [patent_app_number] => 12/423955 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5932 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235795.pdf [firstpage_image] =>[orig_patent_app_number] => 12423955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8561941 [patent_doc_number] => 08336012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Automated timing optimization' [patent_app_type] => utility [patent_app_number] => 12/421198 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1536 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12421198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4647065 [patent_doc_number] => 08024678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-20 [patent_title] => 'Interfacing with a dynamically configurable arithmetic unit' [patent_app_type] => utility [patent_app_number] => 12/416333 [patent_app_country] => US [patent_app_date] => 2009-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7629 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/024/08024678.pdf [firstpage_image] =>[orig_patent_app_number] => 12416333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6366272 [patent_doc_number] => 20100251199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'Method and system for automated convergence of ternary simulation by saturation of deep gates' [patent_app_type] => utility [patent_app_number] => 12/410968 [patent_app_country] => US [patent_app_date] => 2009-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10134 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20100251199.pdf [firstpage_image] =>[orig_patent_app_number] => 12410968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7510720 [patent_doc_number] => 08037436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Circuit verification apparatus, a method of circuit verification and circuit verification program' [patent_app_type] => utility [patent_app_number] => 12/397018 [patent_app_country] => US [patent_app_date] => 2009-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8861 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037436.pdf [firstpage_image] =>[orig_patent_app_number] => 12397018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5529067 [patent_doc_number] => 20090199144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Method of designing semiconductor integrated circuit having function to adjust delay pass and apparatus for supporting design thereof' [patent_app_type] => utility [patent_app_number] => 12/320643 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4340 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20090199144.pdf [firstpage_image] =>[orig_patent_app_number] => 12320643 [rel_patent_id] =>[rel_patent_doc_number] =>)