Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6338648 [patent_doc_number] => 20100199246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Programmable analog tile configuration tool' [patent_app_type] => utility [patent_app_number] => 12/322373 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199246.pdf [firstpage_image] =>[orig_patent_app_number] => 12322373 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/322373
Programmable analog tile configuration tool Jan 29, 2009 Issued
Array ( [id] => 7525091 [patent_doc_number] => 08028261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Method of predicting substrate current in high voltage device' [patent_app_type] => utility [patent_app_number] => 12/344383 [patent_app_country] => US [patent_app_date] => 2008-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2486 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028261.pdf [firstpage_image] =>[orig_patent_app_number] => 12344383 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344383
Method of predicting substrate current in high voltage device Dec 25, 2008 Issued
Array ( [id] => 6302839 [patent_doc_number] => 20100162186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Optimal Distance Based Buffer Tree for Data Path and Clock' [patent_app_type] => utility [patent_app_number] => 12/340193 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20100162186.pdf [firstpage_image] =>[orig_patent_app_number] => 12340193 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/340193
Optimal distance based buffer tree for data path and clock Dec 18, 2008 Issued
Array ( [id] => 7993409 [patent_doc_number] => 08079013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-13 [patent_title] => 'Hardware description interface for a high-level modeling system' [patent_app_type] => utility [patent_app_number] => 12/340473 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 9656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/079/08079013.pdf [firstpage_image] =>[orig_patent_app_number] => 12340473 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/340473
Hardware description interface for a high-level modeling system Dec 18, 2008 Issued
Array ( [id] => 6032182 [patent_doc_number] => 20110055794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Method for Modeling a Magnetic Tunnel Junction with Spin-Polarized Current Writing' [patent_app_type] => utility [patent_app_number] => 12/809991 [patent_app_country] => US [patent_app_date] => 2008-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6738 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055794.pdf [firstpage_image] =>[orig_patent_app_number] => 12809991 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/809991
Method for modeling a magnetic tunnel junction with spin-polarized current writing Dec 15, 2008 Issued
Array ( [id] => 6451149 [patent_doc_number] => 20100153895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'TIMING ERROR SAMPLING GENERATOR, CRITICAL PATH MONITOR FOR HOLD AND SETUP VIOLATIONS OF AN INTEGRATED CIRCUIT AND A METHOD OF TIMING TESTING' [patent_app_type] => utility [patent_app_number] => 12/334403 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5041 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153895.pdf [firstpage_image] =>[orig_patent_app_number] => 12334403 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334403
Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing Dec 11, 2008 Issued
Array ( [id] => 6466008 [patent_doc_number] => 20100146469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'SYSTEM AND METHOD FOR SELECTING GATES IN A LOGIC BLOCK' [patent_app_type] => utility [patent_app_number] => 12/332013 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146469.pdf [firstpage_image] =>[orig_patent_app_number] => 12332013 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332013
System and method for selecting gates in a logic block Dec 9, 2008 Issued
Array ( [id] => 8787181 [patent_doc_number] => 08434037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Sub-circuit pattern recognition in integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/323483 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8694 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12323483 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/323483
Sub-circuit pattern recognition in integrated circuit design Nov 25, 2008 Issued
Array ( [id] => 7510731 [patent_doc_number] => 08037442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Method and apparatus for scaling I/O-cell placement during die-size optimization' [patent_app_type] => utility [patent_app_number] => 12/323883 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6824 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037442.pdf [firstpage_image] =>[orig_patent_app_number] => 12323883 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/323883
Method and apparatus for scaling I/O-cell placement during die-size optimization Nov 25, 2008 Issued
Array ( [id] => 5332886 [patent_doc_number] => 20090113363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'METHOD AND SYSTEM FOR CREATING A BOOLEAN MODEL OF MULTI-PATH AND MULTI-STRENGTH SIGNALS FOR VERIFICATION' [patent_app_type] => utility [patent_app_number] => 12/260353 [patent_app_country] => US [patent_app_date] => 2008-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3282 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113363.pdf [firstpage_image] =>[orig_patent_app_number] => 12260353 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/260353
Method and system for creating a boolean model of multi-path and multi-strength signals for verification Oct 28, 2008 Issued
Array ( [id] => 4621762 [patent_doc_number] => 08001493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions' [patent_app_type] => utility [patent_app_number] => 12/199161 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001493.pdf [firstpage_image] =>[orig_patent_app_number] => 12199161 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199161
Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions Aug 26, 2008 Issued
Array ( [id] => 6557253 [patent_doc_number] => 20100205573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'LAYOUT MODIFICATION ENGINE FOR MODIFYING A CIRCUIT LAYOUT COMPRISING FIXED AND FREE LAYOUT ENTITIES' [patent_app_type] => utility [patent_app_number] => 12/667333 [patent_app_country] => US [patent_app_date] => 2008-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7071 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205573.pdf [firstpage_image] =>[orig_patent_app_number] => 12667333 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/667333
LAYOUT MODIFICATION ENGINE FOR MODIFYING A CIRCUIT LAYOUT COMPRISING FIXED AND FREE LAYOUT ENTITIES Jul 3, 2008 Abandoned
Array ( [id] => 4586265 [patent_doc_number] => 07856609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Using constraints in design verification' [patent_app_type] => utility [patent_app_number] => 12/164781 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4156 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/856/07856609.pdf [firstpage_image] =>[orig_patent_app_number] => 12164781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164781
Using constraints in design verification Jun 29, 2008 Issued
Array ( [id] => 4722839 [patent_doc_number] => 20080244471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'SYSTEM AND METHOD OF CUSTOMIZING AN EXISTING PROCESSOR DESIGN HAVING AN EXISTING PROCESSOR INSTRUCTION SET ARCHITECTURE WITH INSTRUCTION EXTENSIONS' [patent_app_type] => utility [patent_app_number] => 12/135563 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 22847 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244471.pdf [firstpage_image] =>[orig_patent_app_number] => 12135563 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135563
System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions Jun 8, 2008 Issued
Array ( [id] => 4722936 [patent_doc_number] => 20080244506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'SYSTEM AND METHOD OF DESIGNING INSTRUCTION EXTENSIONS TO SUPPLEMENT AN EXISTING PROCESSOR INSTRUCTION SET ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/135502 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 22836 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244506.pdf [firstpage_image] =>[orig_patent_app_number] => 12135502 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135502
System and method of designing instruction extensions to supplement an existing processor instruction set architecture Jun 8, 2008 Issued
Array ( [id] => 4826337 [patent_doc_number] => 20080229260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'STRUCTURE FOR AUTOMATED TRANSISTOR TUNING IN AN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/130476 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4013 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229260.pdf [firstpage_image] =>[orig_patent_app_number] => 12130476 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130476
Structure for automated transistor tuning in an integrated circuit design May 29, 2008 Issued
Array ( [id] => 4826352 [patent_doc_number] => 20080229266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees' [patent_app_type] => utility [patent_app_number] => 12/129773 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9490 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229266.pdf [firstpage_image] =>[orig_patent_app_number] => 12129773 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129773
Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees May 29, 2008 Abandoned
Array ( [id] => 7548058 [patent_doc_number] => 08056039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Interconnect structure for integrated circuits having improved electromigration characteristics' [patent_app_type] => utility [patent_app_number] => 12/128973 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6060 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/056/08056039.pdf [firstpage_image] =>[orig_patent_app_number] => 12128973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128973
Interconnect structure for integrated circuits having improved electromigration characteristics May 28, 2008 Issued
Array ( [id] => 5572884 [patent_doc_number] => 20090140245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Structure for a Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS Process' [patent_app_type] => utility [patent_app_number] => 12/128273 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4428 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140245.pdf [firstpage_image] =>[orig_patent_app_number] => 12128273 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128273
Structure for a Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS Process May 27, 2008 Abandoned
Array ( [id] => 4794069 [patent_doc_number] => 20080295043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Automatic Error Diagnosis and Correction for RTL Designs' [patent_app_type] => utility [patent_app_number] => 12/127523 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9610 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20080295043.pdf [firstpage_image] =>[orig_patent_app_number] => 12127523 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127523
Automatic error diagnosis and correction for RTL designs May 26, 2008 Issued
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