Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5491960 [patent_doc_number] => 20090293031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'Replicating Timing Data in Static Timing Analysis Operation' [patent_app_type] => utility [patent_app_number] => 12/126053 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20090293031.pdf [firstpage_image] =>[orig_patent_app_number] => 12126053 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126053
Replicating timing data in static timing analysis operation May 22, 2008 Issued
Array ( [id] => 5363062 [patent_doc_number] => 20090037856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'SIMULATION METHOD AND COMPUTER-READABLE STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/126063 [patent_app_country] => US [patent_app_date] => 2008-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5693 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037856.pdf [firstpage_image] =>[orig_patent_app_number] => 12126063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/126063
Simulation method and computer-readable storage medium storing program for causing computer to analyze circuit operation using cell characteristics affected by environment May 22, 2008 Issued
Array ( [id] => 8011115 [patent_doc_number] => 08086976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Methods for statistical slew propagation during block-based statistical static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/121023 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6158 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086976.pdf [firstpage_image] =>[orig_patent_app_number] => 12121023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121023
Methods for statistical slew propagation during block-based statistical static timing analysis May 14, 2008 Issued
Array ( [id] => 5554067 [patent_doc_number] => 20090288053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'METHODS OF CELL ASSOCIATION FOR AUTOMATED DISTANCE MANAGEMENT IN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/119893 [patent_app_country] => US [patent_app_date] => 2008-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3810 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20090288053.pdf [firstpage_image] =>[orig_patent_app_number] => 12119893 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/119893
METHODS OF CELL ASSOCIATION FOR AUTOMATED DISTANCE MANAGEMENT IN INTEGRATED CIRCUIT DESIGN May 12, 2008 Abandoned
Array ( [id] => 4841732 [patent_doc_number] => 20080282218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Method for Designing Mask' [patent_app_type] => utility [patent_app_number] => 12/118123 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2710 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282218.pdf [firstpage_image] =>[orig_patent_app_number] => 12118123 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/118123
Method for designing mask including forming a mesh dummy pattern May 8, 2008 Issued
Array ( [id] => 9532671 [patent_doc_number] => 08756557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Techniques for use with automated circuit design and simulations' [patent_app_type] => utility [patent_app_number] => 12/117693 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 18213 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12117693 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117693
Techniques for use with automated circuit design and simulations May 7, 2008 Issued
Array ( [id] => 4951247 [patent_doc_number] => 20080307373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Apparatus, method and computer program for managing circuit optimization information' [patent_app_type] => utility [patent_app_number] => 12/150566 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6257 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307373.pdf [firstpage_image] =>[orig_patent_app_number] => 12150566 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/150566
Apparatus, method and computer program for managing circuit optimization information Apr 28, 2008 Issued
Array ( [id] => 5560177 [patent_doc_number] => 20090271754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'METHOD AND APPARATUS FOR COMPUTING A DETAILED ROUTABILITY ESTIMATION' [patent_app_type] => utility [patent_app_number] => 12/108123 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6844 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20090271754.pdf [firstpage_image] =>[orig_patent_app_number] => 12108123 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108123
Method and apparatus for computing a detailed routability estimation Apr 22, 2008 Issued
Array ( [id] => 4700400 [patent_doc_number] => 20080222584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Method in a Computer-aided Design System for Generating a Functional Design Model of a Test Structure' [patent_app_type] => utility [patent_app_number] => 12/106373 [patent_app_country] => US [patent_app_date] => 2008-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9323 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222584.pdf [firstpage_image] =>[orig_patent_app_number] => 12106373 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/106373
Method in a Computer-aided Design System for Generating a Functional Design Model of a Test Structure Apr 20, 2008 Abandoned
Array ( [id] => 4814694 [patent_doc_number] => 20080195325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'SYSTEM AND COMPUTER PROGRAM FOR EFFICIENT CELL FAILURE RATE ESTIMATION IN CELL ARRAYS' [patent_app_type] => utility [patent_app_number] => 12/103804 [patent_app_country] => US [patent_app_date] => 2008-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4139 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195325.pdf [firstpage_image] =>[orig_patent_app_number] => 12103804 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/103804
SYSTEM AND COMPUTER PROGRAM FOR EFFICIENT CELL FAILURE RATE ESTIMATION IN CELL ARRAYS Apr 15, 2008 Abandoned
Array ( [id] => 4447712 [patent_doc_number] => 07930668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-19 [patent_title] => 'Placement and routing using inhibited overlap of expanded areas' [patent_app_type] => utility [patent_app_number] => 12/099223 [patent_app_country] => US [patent_app_date] => 2008-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3864 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930668.pdf [firstpage_image] =>[orig_patent_app_number] => 12099223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099223
Placement and routing using inhibited overlap of expanded areas Apr 7, 2008 Issued
Array ( [id] => 4455157 [patent_doc_number] => 07966589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Structure for dynamic latch state saving device and protocol' [patent_app_type] => utility [patent_app_number] => 12/099423 [patent_app_country] => US [patent_app_date] => 2008-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3371 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966589.pdf [firstpage_image] =>[orig_patent_app_number] => 12099423 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099423
Structure for dynamic latch state saving device and protocol Apr 7, 2008 Issued
Array ( [id] => 9611792 [patent_doc_number] => 08788981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Method of OPC model building, information-processing apparatus, and method of determining process conditions of semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/062133 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4962 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12062133 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062133
Method of OPC model building, information-processing apparatus, and method of determining process conditions of semiconductor device Apr 2, 2008 Issued
Array ( [id] => 4889152 [patent_doc_number] => 20080263484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Layout verification program, layout data and cell data' [patent_app_type] => utility [patent_app_number] => 12/078613 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5189 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263484.pdf [firstpage_image] =>[orig_patent_app_number] => 12078613 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078613
Layout verification program, layout data and cell data Apr 1, 2008 Abandoned
Array ( [id] => 5475169 [patent_doc_number] => 20090248335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'Method and System for the Calculation of the Sensitivities of an Electrical Parameter of an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/059163 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20090248335.pdf [firstpage_image] =>[orig_patent_app_number] => 12059163 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/059163
Method and system for the calculation of the sensitivities of an electrical parameter of an integrated circuit Mar 30, 2008 Issued
Array ( [id] => 4558656 [patent_doc_number] => 07890916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-15 [patent_title] => 'Debugging using a virtual file system interface' [patent_app_type] => utility [patent_app_number] => 12/055163 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9613 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890916.pdf [firstpage_image] =>[orig_patent_app_number] => 12055163 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055163
Debugging using a virtual file system interface Mar 24, 2008 Issued
Array ( [id] => 8023017 [patent_doc_number] => 08141028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Structure for identifying and implementing flexible logic block logic for easy engineering changes' [patent_app_type] => utility [patent_app_number] => 12/054835 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5046 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141028.pdf [firstpage_image] =>[orig_patent_app_number] => 12054835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054835
Structure for identifying and implementing flexible logic block logic for easy engineering changes Mar 24, 2008 Issued
Array ( [id] => 4592224 [patent_doc_number] => 07836418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Method and system for achieving power optimization in a hierarchical netlist' [patent_app_type] => utility [patent_app_number] => 12/053923 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2602 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836418.pdf [firstpage_image] =>[orig_patent_app_number] => 12053923 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053923
Method and system for achieving power optimization in a hierarchical netlist Mar 23, 2008 Issued
Array ( [id] => 4722912 [patent_doc_number] => 20080244492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'APPARATUS AND METHOD FOR DESIGNING SYSTEM, AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/048503 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5912 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244492.pdf [firstpage_image] =>[orig_patent_app_number] => 12048503 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048503
APPARATUS AND METHOD FOR DESIGNING SYSTEM, AND COMPUTER READABLE MEDIUM Mar 13, 2008 Abandoned
Array ( [id] => 7553302 [patent_doc_number] => 08065644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-22 [patent_title] => 'Reducing susceptibility of circuit designs to single event upsets' [patent_app_type] => utility [patent_app_number] => 12/048593 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5972 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065644.pdf [firstpage_image] =>[orig_patent_app_number] => 12048593 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048593
Reducing susceptibility of circuit designs to single event upsets Mar 13, 2008 Issued
Menu