Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4817062 [patent_doc_number] => 20080224321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'CELL DATA FOR SPARE CELL, METHOD OF DESIGNING A SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/046483 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3844 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20080224321.pdf [firstpage_image] =>[orig_patent_app_number] => 12046483 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/046483
CELL DATA FOR SPARE CELL, METHOD OF DESIGNING A SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT Mar 11, 2008 Abandoned
Array ( [id] => 7972393 [patent_doc_number] => 07941775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Arbitrary waveform propagation through a logic gate using timing analysis results' [patent_app_type] => utility [patent_app_number] => 12/044223 [patent_app_country] => US [patent_app_date] => 2008-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941775.pdf [firstpage_image] =>[orig_patent_app_number] => 12044223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/044223
Arbitrary waveform propagation through a logic gate using timing analysis results Mar 6, 2008 Issued
Array ( [id] => 66680 [patent_doc_number] => 07765503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Half cycle common path pessimism removal method' [patent_app_type] => utility [patent_app_number] => 12/039833 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2598 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765503.pdf [firstpage_image] =>[orig_patent_app_number] => 12039833 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039833
Half cycle common path pessimism removal method Feb 28, 2008 Issued
Array ( [id] => 4449098 [patent_doc_number] => 07865850 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-04 [patent_title] => 'Method and apparatus for substrate noise aware floor planning for integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/037843 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 9579 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865850.pdf [firstpage_image] =>[orig_patent_app_number] => 12037843 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037843
Method and apparatus for substrate noise aware floor planning for integrated circuit design Feb 25, 2008 Issued
Array ( [id] => 7543000 [patent_doc_number] => 08060849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Automatic bus routing' [patent_app_type] => utility [patent_app_number] => 12/037453 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3318 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060849.pdf [firstpage_image] =>[orig_patent_app_number] => 12037453 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037453
Automatic bus routing Feb 25, 2008 Issued
Array ( [id] => 7768471 [patent_doc_number] => 08117583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Determining macro blocks terminal for integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 12/036643 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 24379 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117583.pdf [firstpage_image] =>[orig_patent_app_number] => 12036643 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036643
Determining macro blocks terminal for integrated circuit layout Feb 24, 2008 Issued
Array ( [id] => 5381530 [patent_doc_number] => 20090193369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'PROCESS FOR DESIGN OF SEMICONDUCTOR CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/022860 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3977 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193369.pdf [firstpage_image] =>[orig_patent_app_number] => 12022860 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/022860
Process for design of semiconductor circuits Jan 29, 2008 Issued
Array ( [id] => 5381546 [patent_doc_number] => 20090193385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'Method of checking and correcting mask pattern' [patent_app_type] => utility [patent_app_number] => 12/019640 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4882 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193385.pdf [firstpage_image] =>[orig_patent_app_number] => 12019640 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/019640
Method of checking and correcting mask pattern Jan 24, 2008 Issued
Array ( [id] => 27588 [patent_doc_number] => 07802217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-21 [patent_title] => 'Leakage power optimization considering gate input activity and timing slack' [patent_app_type] => utility [patent_app_number] => 12/011310 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802217.pdf [firstpage_image] =>[orig_patent_app_number] => 12011310 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/011310
Leakage power optimization considering gate input activity and timing slack Jan 24, 2008 Issued
Array ( [id] => 4443740 [patent_doc_number] => 07900163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method and apparatus for identifying redundant scan elements' [patent_app_type] => utility [patent_app_number] => 12/018410 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900163.pdf [firstpage_image] =>[orig_patent_app_number] => 12018410 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018410
Method and apparatus for identifying redundant scan elements Jan 22, 2008 Issued
Array ( [id] => 8183361 [patent_doc_number] => 08181148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Method for identifying and implementing flexible logic block logic for easy engineering changes' [patent_app_type] => utility [patent_app_number] => 12/014240 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4328 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/181/08181148.pdf [firstpage_image] =>[orig_patent_app_number] => 12014240 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/014240
Method for identifying and implementing flexible logic block logic for easy engineering changes Jan 14, 2008 Issued
Array ( [id] => 9826156 [patent_doc_number] => 08935651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-13 [patent_title] => 'Methods and apparatus for data path cluster optimization' [patent_app_type] => utility [patent_app_number] => 11/966790 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 9717 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11966790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/966790
Methods and apparatus for data path cluster optimization Dec 27, 2007 Issued
Array ( [id] => 5273731 [patent_doc_number] => 20090077507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Method of Generating Technology File for Integrated Circuit Design Tools' [patent_app_type] => utility [patent_app_number] => 11/966570 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077507.pdf [firstpage_image] =>[orig_patent_app_number] => 11966570 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/966570
Method of generating technology file for integrated circuit design tools Dec 27, 2007 Issued
Array ( [id] => 4500769 [patent_doc_number] => 07904853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'Pattern signature' [patent_app_type] => utility [patent_app_number] => 11/965680 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904853.pdf [firstpage_image] =>[orig_patent_app_number] => 11965680 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965680
Pattern signature Dec 26, 2007 Issued
Array ( [id] => 4592929 [patent_doc_number] => 07853905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Performing early DFT-aware prototyping of a design' [patent_app_type] => utility [patent_app_number] => 11/965700 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4377 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853905.pdf [firstpage_image] =>[orig_patent_app_number] => 11965700 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965700
Performing early DFT-aware prototyping of a design Dec 26, 2007 Issued
Array ( [id] => 4616655 [patent_doc_number] => 07992108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Impurity concentration distribution predicting method and program for deciding impurity concentration distribution' [patent_app_type] => utility [patent_app_number] => 11/964300 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6131 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 482 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/992/07992108.pdf [firstpage_image] =>[orig_patent_app_number] => 11964300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964300
Impurity concentration distribution predicting method and program for deciding impurity concentration distribution Dec 25, 2007 Issued
Array ( [id] => 375063 [patent_doc_number] => 07475371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Method and system for case-splitting on nodes in a symbolic simulation framework' [patent_app_type] => utility [patent_app_number] => 11/963290 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5189 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475371.pdf [firstpage_image] =>[orig_patent_app_number] => 11963290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/963290
Method and system for case-splitting on nodes in a symbolic simulation framework Dec 20, 2007 Issued
Array ( [id] => 340627 [patent_doc_number] => 07506290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Method and system for case-splitting on nodes in a symbolic simulation framework' [patent_app_type] => utility [patent_app_number] => 11/963264 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5169 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506290.pdf [firstpage_image] =>[orig_patent_app_number] => 11963264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/963264
Method and system for case-splitting on nodes in a symbolic simulation framework Dec 20, 2007 Issued
Array ( [id] => 5548355 [patent_doc_number] => 20090158232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'CIRCUIT ARRANGEMENTS AND ASSOCIATED APPARATUS AND METHODS' [patent_app_type] => utility [patent_app_number] => 11/958280 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10117 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158232.pdf [firstpage_image] =>[orig_patent_app_number] => 11958280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958280
Circuit arrangements and associated apparatus and methods Dec 16, 2007 Issued
Array ( [id] => 5548354 [patent_doc_number] => 20090158231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same' [patent_app_type] => utility [patent_app_number] => 11/955580 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5687 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158231.pdf [firstpage_image] =>[orig_patent_app_number] => 11955580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955580
Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Dec 12, 2007 Issued
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