Anne Marie Sabrina Wehbe

Array ( [id] => 5548354 [patent_doc_number] => 20090158231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same' [patent_app_type] => utility [patent_app_number] => 11/955580 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5687 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158231.pdf [firstpage_image] =>[orig_patent_app_number] => 11955580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5548353 [patent_doc_number] => 20090158230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'DETERMINING ALLOWABLE ANTENNA AREA AS FUNCTION OF TOTAL GATE INSULATOR AREA FOR SOI TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 11/955653 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2795 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158230.pdf [firstpage_image] =>[orig_patent_app_number] => 11955653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4869168 [patent_doc_number] => 20080148202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Circuit pattern design supporting system and circuit pattern designing method' [patent_app_type] => utility [patent_app_number] => 12/000420 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6010 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148202.pdf [firstpage_image] =>[orig_patent_app_number] => 12000420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5577326 [patent_doc_number] => 20090144688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Systems and Methods for Probabilistic Interconnect Planning' [patent_app_type] => utility [patent_app_number] => 11/949583 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7523 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144688.pdf [firstpage_image] =>[orig_patent_app_number] => 11949583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8220456 [patent_doc_number] => 08196088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Method and structure for screening NFET-to-PFET device performance offsets within a CMOS process' [patent_app_type] => utility [patent_app_number] => 11/949066 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3944 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/196/08196088.pdf [firstpage_image] =>[orig_patent_app_number] => 11949066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5577315 [patent_doc_number] => 20090144677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Design Structure for a Circuit and Method to Measure Threshold Voltage Distributions in SRAM Devices' [patent_app_type] => utility [patent_app_number] => 11/947180 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2251 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144677.pdf [firstpage_image] =>[orig_patent_app_number] => 11947180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7537760 [patent_doc_number] => 08051403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus' [patent_app_type] => utility [patent_app_number] => 11/943170 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 10373 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051403.pdf [firstpage_image] =>[orig_patent_app_number] => 11943170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4447682 [patent_doc_number] => 07930656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'System and method for making photomasks' [patent_app_type] => utility [patent_app_number] => 11/940270 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9834 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930656.pdf [firstpage_image] =>[orig_patent_app_number] => 11940270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 108170 [patent_doc_number] => 07725868 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-25 [patent_title] => 'Method and apparatus for facilitating signal routing within a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/983550 [patent_app_country] => US [patent_app_date] => 2007-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4175 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725868.pdf [firstpage_image] =>[orig_patent_app_number] => 11983550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4774257 [patent_doc_number] => 20080059919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'COMPUTER PROGRAM FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD' [patent_app_type] => utility [patent_app_number] => 11/936673 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3007 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059919.pdf [firstpage_image] =>[orig_patent_app_number] => 11936673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 108155 [patent_doc_number] => 07725855 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-25 [patent_title] => 'Symmetry-based optimization for the physical synthesis of programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/981910 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725855.pdf [firstpage_image] =>[orig_patent_app_number] => 11981910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4919296 [patent_doc_number] => 20080067608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Storage Elements with Disguised Configurations and Methods of Using the Same' [patent_app_type] => utility [patent_app_number] => 11/928663 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9719 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067608.pdf [firstpage_image] =>[orig_patent_app_number] => 11928663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5351676 [patent_doc_number] => 20090007037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures' [patent_app_type] => utility [patent_app_number] => 11/925413 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5588 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007037.pdf [firstpage_image] =>[orig_patent_app_number] => 11925413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 47971 [patent_doc_number] => 07784009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Electrically programmable π-shaped fuse structures and design process therefore' [patent_app_type] => utility [patent_app_number] => 11/923833 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 5207 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784009.pdf [firstpage_image] =>[orig_patent_app_number] => 11923833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 66695 [patent_doc_number] => 07765511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-27 [patent_title] => 'Compensation for performance variation in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/975960 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4478 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765511.pdf [firstpage_image] =>[orig_patent_app_number] => 11975960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5454679 [patent_doc_number] => 20090070716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'SYSTEM AND METHOD FOR OPTIMIZATION AND PREDICATION OF VARIABILITY AND YIELD IN INTEGRATED CIRUITS' [patent_app_type] => utility [patent_app_number] => 11/853930 [patent_app_country] => US [patent_app_date] => 2007-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070716.pdf [firstpage_image] =>[orig_patent_app_number] => 11853930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4578004 [patent_doc_number] => 07823100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Generating self-checking test cases from a reduced case analysis graph using path constraints' [patent_app_type] => utility [patent_app_number] => 11/853390 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7868 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823100.pdf [firstpage_image] =>[orig_patent_app_number] => 11853390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5454685 [patent_doc_number] => 20090070722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'METHOD FOR GENERATING DEVICE MODEL OVERRIDES THROUGH THE USE OF ON-CHIP PARAMETRIC MEASUREMENT MACROS' [patent_app_type] => utility [patent_app_number] => 11/851073 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3369 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070722.pdf [firstpage_image] =>[orig_patent_app_number] => 11851073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4658800 [patent_doc_number] => 20080027662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium' [patent_app_type] => utility [patent_app_number] => 11/882293 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9337 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20080027662.pdf [firstpage_image] =>[orig_patent_app_number] => 11882293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4690157 [patent_doc_number] => 20080034338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Timing analysis method and device' [patent_app_type] => utility [patent_app_number] => 11/878264 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034338.pdf [firstpage_image] =>[orig_patent_app_number] => 11878264 [rel_patent_id] =>[rel_patent_doc_number] =>)